inorder: squash on memory stall

[gem5.git] / src / cpu / BaseCPU.py

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 75114053e7a8f3de2c02beea66591414b66dfaf5..ac734e5ac409c0282d5386c6ef8546884f210125 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -59,6 +59,10 @@ elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
     if buildEnv['FULL_SYSTEM']:
         from ArmInterrupts import ArmInterrupts
+elif buildEnv['TARGET_ISA'] == 'power':
+    from PowerTLB import PowerTLB
+    if buildEnv['FULL_SYSTEM']:
+        from PowerInterrupts import PowerInterrupts
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -116,6 +120,13 @@ class BaseCPU(MemObject):
         if buildEnv['FULL_SYSTEM']:
             interrupts = Param.ArmInterrupts(
                     ArmInterrupts(), "Interrupt Controller")
+    elif buildEnv['TARGET_ISA'] == 'power':
+        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+        dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
+        itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
+        if buildEnv['FULL_SYSTEM']:
+            interrupts = Param.PowerInterrupts(
+                    PowerInterrupts(), "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']