-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
+# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
+# Rick Strong
-from m5.SimObject import SimObject
+import sys
+
+from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
-from m5 import build_env
+
from Bus import Bus
-import sys
+from InstTracer import InstTracer
+from ExeTracer import ExeTracer
+from MemObject import MemObject
-if build_env['FULL_SYSTEM']:
- if build_env['TARGET_ISA'] == 'alpha':
- from AlphaTLB import AlphaDTB, AlphaITB
+default_tracer = ExeTracer()
- if build_env['TARGET_ISA'] == 'sparc':
- from SparcTLB import SparcDTB, SparcITB
+if buildEnv['TARGET_ISA'] == 'alpha':
+ from AlphaTLB import AlphaDTB, AlphaITB
+ if buildEnv['FULL_SYSTEM']:
+ from AlphaInterrupts import AlphaInterrupts
+elif buildEnv['TARGET_ISA'] == 'sparc':
+ from SparcTLB import SparcTLB
+ if buildEnv['FULL_SYSTEM']:
+ from SparcInterrupts import SparcInterrupts
+elif buildEnv['TARGET_ISA'] == 'x86':
+ from X86TLB import X86TLB
+ if buildEnv['FULL_SYSTEM']:
+ from X86LocalApic import X86LocalApic
+elif buildEnv['TARGET_ISA'] == 'mips':
+ from MipsTLB import MipsTLB
+ if buildEnv['FULL_SYSTEM']:
+ from MipsInterrupts import MipsInterrupts
+elif buildEnv['TARGET_ISA'] == 'arm':
+ from ArmTLB import ArmTLB
+ if buildEnv['FULL_SYSTEM']:
+ from ArmInterrupts import ArmInterrupts
+elif buildEnv['TARGET_ISA'] == 'power':
+ from PowerTLB import PowerTLB
+ if buildEnv['FULL_SYSTEM']:
+ from PowerInterrupts import PowerInterrupts
-class BaseCPU(SimObject):
+class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
system = Param.System(Parent.any, "system object")
- cpu_id = Param.Int("CPU identifier")
+ cpu_id = Param.Int(-1, "CPU identifier")
+ numThreads = Param.Unsigned(1, "number of HW thread contexts")
+
+ function_trace = Param.Bool(False, "Enable function trace")
+ function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+ checker = Param.BaseCPU(NULL, "checker CPU")
+
+ do_checkpoint_insts = Param.Bool(True,
+ "enable checkpoint pseudo instructions")
+ do_statistics_insts = Param.Bool(True,
+ "enable statistics pseudo instructions")
- if build_env['FULL_SYSTEM']:
+ if buildEnv['FULL_SYSTEM']:
+ profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions")
- do_checkpoint_insts = Param.Bool(True,
- "enable checkpoint pseudo instructions")
- do_statistics_insts = Param.Bool(True,
- "enable statistics pseudo instructions")
-
- if build_env['TARGET_ISA'] == 'sparc':
- dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
- itb = Param.SparcITB(SparcITB(), "Instruction TLB")
- elif build_env['TARGET_ISA'] == 'alpha':
- dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
- itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
- else:
- print "Unknown architecture, can't pick TLBs"
- sys.exit(1)
else:
workload = VectorParam.Process("processes to run")
+ if buildEnv['TARGET_ISA'] == 'sparc':
+ dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
+ itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ interrupts = Param.SparcInterrupts(
+ SparcInterrupts(), "Interrupt Controller")
+ elif buildEnv['TARGET_ISA'] == 'alpha':
+ dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
+ itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ interrupts = Param.AlphaInterrupts(
+ AlphaInterrupts(), "Interrupt Controller")
+ elif buildEnv['TARGET_ISA'] == 'x86':
+ dtb = Param.X86TLB(X86TLB(), "Data TLB")
+ itb = Param.X86TLB(X86TLB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+ interrupts = \
+ Param.X86LocalApic(_localApic, "Interrupt Controller")
+ elif buildEnv['TARGET_ISA'] == 'mips':
+ dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
+ itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ interrupts = Param.MipsInterrupts(
+ MipsInterrupts(), "Interrupt Controller")
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
+ itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ interrupts = Param.ArmInterrupts(
+ ArmInterrupts(), "Interrupt Controller")
+ elif buildEnv['TARGET_ISA'] == 'power':
+ UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+ dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
+ itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
+ if buildEnv['FULL_SYSTEM']:
+ interrupts = Param.PowerInterrupts(
+ PowerInterrupts(), "Interrupt Controller")
+ else:
+ print "Don't know what TLB to use for ISA %s" % \
+ buildEnv['TARGET_ISA']
+ sys.exit(1)
+
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
max_insts_any_thread = Param.Counter(0,
clock = Param.Clock('1t', "clock speed")
phase = Param.Latency('0ns', "clock phase")
- _mem_ports = []
+ tracer = Param.InstTracer(default_tracer, "Instruction tracer")
+
+ _cached_ports = []
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+ _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+ _uncached_ports = []
+ if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
+ _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
- def connectMemPorts(self, bus):
- for p in self._mem_ports:
+ def connectCachedPorts(self, bus):
+ for p in self._cached_ports:
exec('self.%s = bus.port' % p)
- def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) == 2)
+ def connectUncachedPorts(self, bus):
+ for p in self._uncached_ports:
+ exec('self.%s = bus.port' % p)
+
+ def connectAllPorts(self, cached_bus, uncached_bus = None):
+ self.connectCachedPorts(cached_bus)
+ if not uncached_bus:
+ uncached_bus = cached_bus
+ self.connectUncachedPorts(uncached_bus)
+
+ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+ assert(len(self._cached_ports) < 7)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
- self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+ self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
+ if buildEnv['FULL_SYSTEM']:
+ if buildEnv['TARGET_ISA'] == 'x86':
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
- def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
- self.addPrivateSplitL1Caches(ic, dc)
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
+ self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = Bus()
- self.connectMemPorts(self.toL2Bus)
+ self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
- self._mem_ports = ['l2cache.mem_side']
+ self._cached_ports = ['l2cache.mem_side']
projects / gem5.git / blobdiff