# Copyright (c) 2005-2008 The Regents of The University of Michigan
+# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
+# Rick Strong
import sys
interrupts = Param.MipsInterrupts(
MipsInterrupts(), "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'arm':
- UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
if buildEnv['FULL_SYSTEM']:
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- _mem_ports = []
+ _cached_ports = []
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+ _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+ _uncached_ports = []
if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
- _mem_ports = ["itb.walker.port",
- "dtb.walker.port",
- "interrupts.pio",
- "interrupts.int_port"]
-
- def connectMemPorts(self, bus):
- for p in self._mem_ports:
- if p != 'physmem_port':
- exec('self.%s = bus.port' % p)
-
- def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) < 6)
+ _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
+
+ def connectCachedPorts(self, bus):
+ for p in self._cached_ports:
+ exec('self.%s = bus.port' % p)
+
+ def connectUncachedPorts(self, bus):
+ for p in self._uncached_ports:
+ exec('self.%s = bus.port' % p)
+
+ def connectAllPorts(self, cached_bus, uncached_bus = None):
+ self.connectCachedPorts(cached_bus)
+ if not uncached_bus:
+ uncached_bus = cached_bus
+ self.connectUncachedPorts(uncached_bus)
+
+ def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+ assert(len(self._cached_ports) < 7)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
- self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
- self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
-
- def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
- self.addPrivateSplitL1Caches(ic, dc)
+ self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
+ if buildEnv['FULL_SYSTEM']:
+ if buildEnv['TARGET_ISA'] == 'x86':
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
+ self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = Bus()
- self.connectMemPorts(self.toL2Bus)
+ self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
- self._mem_ports = ['l2cache.mem_side']
-
- if buildEnv['TARGET_ISA'] == 'mips':
- CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
- CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
- CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
- CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
- CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
- CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
- CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
- CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
- CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
- CP0_Config_AT = Param.Unsigned(0,"No Description")
- CP0_Config_AR = Param.Unsigned(0,"No Description")
- CP0_Config_MT = Param.Unsigned(0,"No Description")
- CP0_Config_VI = Param.Unsigned(0,"No Description")
- CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
- CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
- CP0_Config1_IS = Param.Unsigned(0,"No Description")
- CP0_Config1_IL = Param.Unsigned(0,"No Description")
- CP0_Config1_IA = Param.Unsigned(0,"No Description")
- CP0_Config1_DS = Param.Unsigned(0,"No Description")
- CP0_Config1_DL = Param.Unsigned(0,"No Description")
- CP0_Config1_DA = Param.Unsigned(0,"No Description")
- CP0_Config1_C2 = Param.Bool(False,"No Description")
- CP0_Config1_MD = Param.Bool(False,"No Description")
- CP0_Config1_PC = Param.Bool(False,"No Description")
- CP0_Config1_WR = Param.Bool(False,"No Description")
- CP0_Config1_CA = Param.Bool(False,"No Description")
- CP0_Config1_EP = Param.Bool(False,"No Description")
- CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
- CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
- CP0_Config2_TU = Param.Unsigned(0,"No Description")
- CP0_Config2_TS = Param.Unsigned(0,"No Description")
- CP0_Config2_TL = Param.Unsigned(0,"No Description")
- CP0_Config2_TA = Param.Unsigned(0,"No Description")
- CP0_Config2_SU = Param.Unsigned(0,"No Description")
- CP0_Config2_SS = Param.Unsigned(0,"No Description")
- CP0_Config2_SL = Param.Unsigned(0,"No Description")
- CP0_Config2_SA = Param.Unsigned(0,"No Description")
- CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
- CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
- CP0_Config3_LPA = Param.Bool(False,"No Description")
- CP0_Config3_VEIC = Param.Bool(False,"No Description")
- CP0_Config3_VInt = Param.Bool(False,"No Description")
- CP0_Config3_SP = Param.Bool(False,"No Description")
- CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
- CP0_Config3_SM = Param.Bool(False,"No Description")
- CP0_Config3_TL = Param.Bool(False,"No Description")
- CP0_WatchHi_M = Param.Bool(False,"No Description")
- CP0_PerfCtr_M = Param.Bool(False,"No Description")
- CP0_PerfCtr_W = Param.Bool(False,"No Description")
- CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
- CP0_Config = Param.Unsigned(0,"CP0 Config Register")
- CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
- CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
- CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
+ self._cached_ports = ['l2cache.mem_side']
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