+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005-2008 The Regents of The University of Michigan
# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Authors: Nathan Binkert
# Rick Strong
+# Andreas Hansson
import sys
from m5.params import *
from m5.proxy import *
-from Bus import Bus
+from Bus import CoherentBus
from InstTracer import InstTracer
from ExeTracer import ExeTracer
from MemObject import MemObject
class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
+ cxx_header = "cpu/base.hh"
+
+ @classmethod
+ def export_methods(cls, code):
+ code('''
+ void switchOut();
+ void takeOverFrom(BaseCPU *cpu);
+''')
+
+ def takeOverFrom(self, old_cpu):
+ self._ccObject.takeOverFrom(old_cpu._ccObject)
+
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
numThreads = Param.Unsigned(1, "number of HW thread contexts")
function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
+ function_trace_start = Param.Tick(0, "Tick to start function trace")
checker = Param.BaseCPU(NULL, "checker CPU")
do_statistics_insts = Param.Bool(True,
"enable statistics pseudo instructions")
- if buildEnv['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
- do_quiesce = Param.Bool(True, "enable quiesce instructions")
- else:
- workload = VectorParam.Process("processes to run")
+ profile = Param.Latency('0ns', "trace the kernel stack")
+ do_quiesce = Param.Bool(True, "enable quiesce instructions")
+
+ workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
interrupts = Param.SparcInterrupts(
- SparcInterrupts(), "Interrupt Controller")
+ NULL, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
interrupts = Param.AlphaInterrupts(
- AlphaInterrupts(), "Interrupt Controller")
+ NULL, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'x86':
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
- _localApic = X86LocalApic(pio_addr=0x2000000000000000)
- interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
+ interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'mips':
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
interrupts = Param.MipsInterrupts(
- MipsInterrupts(), "Interrupt Controller")
+ NULL, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'arm':
dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
interrupts = Param.ArmInterrupts(
- ArmInterrupts(), "Interrupt Controller")
+ NULL, "Interrupt Controller")
elif buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
interrupts = Param.PowerInterrupts(
- PowerInterrupts(), "Interrupt Controller")
+ NULL, "Interrupt Controller")
else:
print "Don't know what TLB to use for ISA %s" % \
buildEnv['TARGET_ISA']
"terminate when all threads have reached this load count")
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
- progress_interval = Param.Tick(0,
- "interval to print out the progress message")
+ progress_interval = Param.Frequency('0Hz',
+ "frequency to print out the progress message")
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
- clock = Param.Clock('1t', "clock speed")
- phase = Param.Latency('0ns', "clock phase")
-
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- _cached_ports = []
- if buildEnv['TARGET_ISA'] == 'x86' or \
- (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
- _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+ icache_port = MasterPort("Instruction Port")
+ dcache_port = MasterPort("Data Port")
+ _cached_ports = ['icache_port', 'dcache_port']
- _uncached_ports = []
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ _cached_ports += ["itb.walker.port", "dtb.walker.port"]
+
+ _uncached_slave_ports = []
+ _uncached_master_ports = []
if buildEnv['TARGET_ISA'] == 'x86':
- _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
+ _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
+ _uncached_master_ports += ["interrupts.int_master"]
+
+ def createInterruptController(self):
+ if buildEnv['TARGET_ISA'] == 'sparc':
+ self.interrupts = SparcInterrupts()
+ elif buildEnv['TARGET_ISA'] == 'alpha':
+ self.interrupts = AlphaInterrupts()
+ elif buildEnv['TARGET_ISA'] == 'x86':
+ _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+ self.interrupts = _localApic
+ elif buildEnv['TARGET_ISA'] == 'mips':
+ self.interrupts = MipsInterrupts()
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ self.interrupts = ArmInterrupts()
+ elif buildEnv['TARGET_ISA'] == 'power':
+ self.interrupts = PowerInterrupts()
+ else:
+ print "Don't know what Interrupt Controller to use for ISA %s" % \
+ buildEnv['TARGET_ISA']
+ sys.exit(1)
def connectCachedPorts(self, bus):
for p in self._cached_ports:
- exec('self.%s = bus.port' % p)
+ exec('self.%s = bus.slave' % p)
def connectUncachedPorts(self, bus):
- for p in self._uncached_ports:
- exec('self.%s = bus.port' % p)
+ for p in self._uncached_slave_ports:
+ exec('self.%s = bus.master' % p)
+ for p in self._uncached_master_ports:
+ exec('self.%s = bus.slave' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
self.connectUncachedPorts(uncached_bus)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- assert(len(self._cached_ports) < 7)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['FULL_SYSTEM']:
- if buildEnv['TARGET_ISA'] == 'x86':
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
- elif buildEnv['TARGET_ISA'] == 'arm':
+ else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+ # Checker doesn't need its own tlb caches because it does
+ # functional accesses only
+ if self.checker != NULL:
+ self._cached_ports += ["checker.itb.walker.port", \
+ "checker.dtb.walker.port"]
+
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
- self.toL2Bus = Bus()
+ # Override the default bus clock of 1 GHz and uses the CPU
+ # clock for the L1-to-L2 bus, and also set a width of 32 bytes
+ # (256-bits), which is four times that of the default bus.
+ self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
- self.l2cache.cpu_side = self.toL2Bus.port
+ self.toL2Bus.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
+
+ def addCheckerCpu(self):
+ pass
projects / gem5.git / blobdiff