o3 cpu: remove some unused buggy functions in the lsq

[gem5.git] / src / cpu / BaseCPU.py

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 63f45496841b06d172d0a37ae01e0f9cfc51a5ad..dfbd459fd3ab4882ac774d9d9e58ef11b7dedbee 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -47,7 +47,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from Bus import Bus
+from Bus import CoherentBus
 from InstTracer import InstTracer
 from ExeTracer import ExeTracer
 from MemObject import MemObject
@@ -76,13 +76,25 @@ elif buildEnv['TARGET_ISA'] == 'power':
 class BaseCPU(MemObject):
     type = 'BaseCPU'
     abstract = True
+    cxx_header = "cpu/base.hh"
+
+    @classmethod
+    def export_methods(cls, code):
+        code('''
+    void switchOut();
+    void takeOverFrom(BaseCPU *cpu);
+''')
+
+    def takeOverFrom(self, old_cpu):
+        self._ccObject.takeOverFrom(old_cpu._ccObject)
+
 
     system = Param.System(Parent.any, "system object")
     cpu_id = Param.Int(-1, "CPU identifier")
     numThreads = Param.Unsigned(1, "number of HW thread contexts")
 
     function_trace = Param.Bool(False, "Enable function trace")
-    function_trace_start = Param.Tick(0, "Cycle to start function trace")
+    function_trace_start = Param.Tick(0, "Tick to start function trace")
 
     checker = Param.BaseCPU(NULL, "checker CPU")
 
@@ -139,15 +151,12 @@ class BaseCPU(MemObject):
         "terminate when all threads have reached this load count")
     max_loads_any_thread = Param.Counter(0,
         "terminate when any thread reaches this load count")
-    progress_interval = Param.Tick(0,
-        "interval to print out the progress message")
+    progress_interval = Param.Frequency('0Hz',
+        "frequency to print out the progress message")
 
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    clock = Param.Clock('1t', "clock speed")
-    phase = Param.Latency('0ns', "clock phase")
-
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     icache_port = MasterPort("Instruction Port")
@@ -214,16 +223,23 @@ class BaseCPU(MemObject):
                                        "dtb_walker_cache.mem_side"]
             else:
                 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+
             # Checker doesn't need its own tlb caches because it does
             # functional accesses only
-            if buildEnv['USE_CHECKER']:
+            if self.checker != NULL:
                 self._cached_ports += ["checker.itb.walker.port", \
                                        "checker.dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        self.toL2Bus = Bus()
+        # Override the default bus clock of 1 GHz and uses the CPU
+        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
+        # (256-bits), which is four times that of the default bus.
+        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side
         self._cached_ports = ['l2cache.mem_side']
+
+    def addCheckerCpu(self):
+        pass