o3 cpu: remove some unused buggy functions in the lsq

[gem5.git] / src / cpu / BaseCPU.py

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6e5f6ff1abbf56fc183083781bec40369a2419e1..dfbd459fd3ab4882ac774d9d9e58ef11b7dedbee 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -76,11 +76,7 @@ elif buildEnv['TARGET_ISA'] == 'power':
 class BaseCPU(MemObject):
     type = 'BaseCPU'
     abstract = True
-
-    @classmethod
-    def export_method_cxx_predecls(cls, code):
-        code('#include "cpu/base.hh"')
-
+    cxx_header = "cpu/base.hh"
 
     @classmethod
     def export_methods(cls, code):
@@ -236,7 +232,10 @@ class BaseCPU(MemObject):
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        self.toL2Bus = CoherentBus()
+        # Override the default bus clock of 1 GHz and uses the CPU
+        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
+        # (256-bits), which is four times that of the default bus.
+        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side