# Copyright (c) 2012-2013, 2015-2017 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-# Rick Strong
-# Andreas Hansson
-# Glenn Bergmans
from __future__ import print_function
from m5.proxy import *
from m5.util.fdthelper import *
+from m5.objects.ClockedObject import ClockedObject
from m5.objects.XBar import L2XBar
from m5.objects.InstTracer import InstTracer
from m5.objects.CPUTracers import ExeTracer
-from m5.objects.MemObject import MemObject
from m5.objects.SubSystem import SubSystem
from m5.objects.ClockDomain import *
from m5.objects.Platform import Platform
default_tracer = ExeTracer()
-if buildEnv['TARGET_ISA'] == 'alpha':
- from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
- from m5.objects.AlphaInterrupts import AlphaInterrupts
- from m5.objects.AlphaISA import AlphaISA
- default_isa_class = AlphaISA
-elif buildEnv['TARGET_ISA'] == 'sparc':
+if buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
- from m5.objects.SparcInterrupts import SparcInterrupts
- from m5.objects.SparcISA import SparcISA
- default_isa_class = SparcISA
+ from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
+ from m5.objects.SparcISA import SparcISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'x86':
from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
- from m5.objects.X86LocalApic import X86LocalApic
- from m5.objects.X86ISA import X86ISA
- default_isa_class = X86ISA
+ from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
+ from m5.objects.X86ISA import X86ISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
- from m5.objects.MipsInterrupts import MipsInterrupts
- from m5.objects.MipsISA import MipsISA
- default_isa_class = MipsISA
+ from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
+ from m5.objects.MipsISA import MipsISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'arm':
- from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
- from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
- from m5.objects.ArmInterrupts import ArmInterrupts
- from m5.objects.ArmISA import ArmISA
- default_isa_class = ArmISA
+ from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
+ from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
+ from m5.objects.ArmISA import ArmISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'power':
from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
- from m5.objects.PowerInterrupts import PowerInterrupts
- from m5.objects.PowerISA import PowerISA
- default_isa_class = PowerISA
+ from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
+ from m5.objects.PowerISA import PowerISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'riscv':
from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
- from m5.objects.RiscvInterrupts import RiscvInterrupts
- from m5.objects.RiscvISA import RiscvISA
- default_isa_class = RiscvISA
-
-class BaseCPU(MemObject):
+ from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
+ from m5.objects.RiscvISA import RiscvISA as ArchISA
+else:
+ print("Don't know what object types to use for ISA %s" %
+ buildEnv['TARGET_ISA'])
+ sys.exit(1)
+
+class BaseCPU(ClockedObject):
type = 'BaseCPU'
abstract = True
cxx_header = "cpu/base.hh"
PyBindMethod("flushTLBs"),
PyBindMethod("totalInsts"),
PyBindMethod("scheduleInstStop"),
- PyBindMethod("scheduleLoadStop"),
PyBindMethod("getCurrentInstCount"),
]
do_statistics_insts = Param.Bool(True,
"enable statistics pseudo instructions")
- profile = Param.Latency('0ns', "trace the kernel stack")
- do_quiesce = Param.Bool(True, "enable quiesce instructions")
-
wait_for_remote_gdb = Param.Bool(False,
"Wait for a remote GDB connection");
dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
- if buildEnv['TARGET_ISA'] == 'sparc':
- interrupts = VectorParam.SparcInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.SparcISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'alpha':
- interrupts = VectorParam.AlphaInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.AlphaISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'x86':
- interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
- isa = VectorParam.X86ISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'mips':
- interrupts = VectorParam.MipsInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.MipsISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'arm':
- istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
- dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
- interrupts = VectorParam.ArmInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.ArmISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'power':
+ if buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
- interrupts = VectorParam.PowerInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.PowerISA([], "ISA instance")
- elif buildEnv['TARGET_ISA'] == 'riscv':
- interrupts = VectorParam.RiscvInterrupts(
- [], "Interrupt Controller")
- isa = VectorParam.RiscvISA([], "ISA instance")
- else:
- print("Don't know what TLB to use for ISA %s" %
- buildEnv['TARGET_ISA'])
- sys.exit(1)
+ interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
+ isa = VectorParam.BaseISA([], "ISA instance")
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
"terminate when any thread reaches this inst count")
simpoint_start_insts = VectorParam.Counter([],
"starting instruction counts of simpoints")
- max_loads_all_threads = Param.Counter(0,
- "terminate when all threads have reached this load count")
- max_loads_any_thread = Param.Counter(0,
- "terminate when any thread reaches this load count")
progress_interval = Param.Frequency('0Hz',
"frequency to print out the progress message")
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- icache_port = MasterPort("Instruction Port")
- dcache_port = MasterPort("Data Port")
+ icache_port = RequestPort("Instruction Port")
+ dcache_port = RequestPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
- if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_slave_ports = []
_uncached_master_ports += ["interrupts[0].int_master"]
def createInterruptController(self):
- if buildEnv['TARGET_ISA'] == 'sparc':
- self.interrupts = [SparcInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'alpha':
- self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'x86':
- self.apic_clk_domain = DerivedClockDomain(clk_domain =
- Parent.clk_domain,
- clk_divider = 16)
- self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
- pio_addr=0x2000000000000000)
- for i in range(self.numThreads)]
- _localApic = self.interrupts
- elif buildEnv['TARGET_ISA'] == 'mips':
- self.interrupts = [MipsInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'arm':
- self.interrupts = [ArmInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'power':
- self.interrupts = [PowerInterrupts() for i in range(self.numThreads)]
- elif buildEnv['TARGET_ISA'] == 'riscv':
- self.interrupts = \
- [RiscvInterrupts() for i in range(self.numThreads)]
- else:
- print("Don't know what Interrupt Controller to use for ISA %s" %
- buildEnv['TARGET_ISA'])
- sys.exit(1)
+ self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
def connectCachedPorts(self, bus):
for p in self._cached_ports:
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
# If no ISAs have been created, assume that the user wants the
# default ISA.
if len(self.isa) == 0:
- self.isa = [ default_isa_class() for i in range(self.numThreads) ]
+ self.isa = [ ArchISA() for i in range(self.numThreads) ]
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError("Number of ISA instances doesn't "
warn("Platform not found for device tree generation; " \
"system or multiple CPUs may not start")
- freq = round(self.clk_domain.unproxy(self).clock[0].frequency)
+ freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
node.append(FdtPropertyWords("clock-frequency", freq))
# Unique key for this CPU
cpus_node.append(node)
yield cpus_node
+
+ def __init__(self, **kwargs):
+ super(BaseCPU, self).__init__(**kwargs)
+ self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
projects / gem5.git / blobdiff