sim: Include object header files in SWIG interfaces

[gem5.git] / src / cpu / IntrControl.py

diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py
index eb4b1696bfbbc58c09ab1bca3d0277b53eeacae0..72ea6ccb97adfe1fa8e4916ff27682718371d645 100644 (file)
--- a/src/cpu/IntrControl.py
+++ b/src/cpu/IntrControl.py
@@ -31,4 +31,5 @@ from m5.params import *
 from m5.proxy import *
 class IntrControl(SimObject):
     type = 'IntrControl'
+    cxx_header = "cpu/intr_control.hh"
     sys = Param.System(Parent.any, "the system we are part of")