#
#################################################################
-# CPU model-specific data is contained in cpu_models.py
-# Convert to SCons File node to get path handling
-models_db = File('cpu_models.py')
-# slurp in contents of file
-execfile(models_db.srcnode().abspath)
-
# Template for execute() signature.
exec_sig_template = '''
-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
+virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
+virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
-virtual Fault completeAcc(Packet *pkt, %s *xc,
+virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''
'''
for cpu in temp_cpu_list:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
- print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
+ print >> f, exec_sig_template % { 'type' : xc_type }
print >> f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
# Generate string that gets printed when header is rebuilt
def gen_sigs_string(target, source, env):
- return "Generating static_inst_exec_sigs.hh: " \
+ return " [GENERATE] static_inst_exec_sigs.hh: " \
+ ', '.join(temp_cpu_list)
# Add command to generate header to environment.
-env.Command('static_inst_exec_sigs.hh', models_db,
+env.Command('static_inst_exec_sigs.hh', (),
Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = temp_cpu_list))
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
+SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
+Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
SimObject('LegionTrace.py')
Source('legiontrace.cc')
-if env['TARGET_ISA'] == 'x86':
- SimObject('NativeTrace.py')
- Source('nativetrace.cc')
-
if env['USE_CHECKER']:
Source('checker/cpu.cc')
TraceFlag('Checker')
print i,
print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
-# Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308
-else:
- Dir('checker')
TraceFlag('Activity')
TraceFlag('Commit')
TraceFlag('ExecEnable')
TraceFlag('ExecCPSeq')
TraceFlag('ExecEffAddr')
+TraceFlag('ExecFaulting', 'Trace faulting instructions')
TraceFlag('ExecFetchSeq')
TraceFlag('ExecOpClass')
TraceFlag('ExecRegDelta')
TraceFlag('ExecSymbol')
TraceFlag('ExecThread')
TraceFlag('ExecTicks')
+TraceFlag('ExecMicro')
+TraceFlag('ExecMacro')
TraceFlag('Fetch')
TraceFlag('IntrControl')
TraceFlag('PCEvent')
TraceFlag('Quiesce')
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
- 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])
+ 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
+CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
+ 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])