SCons: Cleanup SCons output during compile

[gem5.git] / src / cpu / SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 854db9f12db02a43bb6d1faf9ae3b5bbfe96547a..35e92a1b69ca17284836877760a954147a1ac351 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -40,12 +40,6 @@ Import('*')
 #
 #################################################################
 
-# CPU model-specific data is contained in cpu_models.py
-# Convert to SCons File node to get path handling
-models_db = File('cpu_models.py')
-# slurp in contents of file
-execfile(models_db.srcnode().abspath)
-
 # Template for execute() signature.
 exec_sig_template = '''
 virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
@@ -56,8 +50,6 @@ virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
 virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
                           Trace::InstRecord *traceData) const
 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
-virtual int memAccSize(%(type)s *xc)
-{ panic("memAccSize not defined!"); M5_DUMMY_RETURN };
 '''
 
 mem_ini_sig_template = '''
@@ -95,11 +87,11 @@ def gen_cpu_exec_signatures(target, source, env):
 
 # Generate string that gets printed when header is rebuilt
 def gen_sigs_string(target, source, env):
-    return "Generating static_inst_exec_sigs.hh: " \
+    return " [GENERATE] static_inst_exec_sigs.hh: " \
            + ', '.join(temp_cpu_list)
 
 # Add command to generate header to environment.
-env.Command('static_inst_exec_sigs.hh', models_db,
+env.Command('static_inst_exec_sigs.hh', (),
             Action(gen_cpu_exec_signatures, gen_sigs_string,
                    varlist = temp_cpu_list))
 
@@ -114,6 +106,7 @@ SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
 SimObject('ExeTracer.py')
 SimObject('IntelTrace.py')
+SimObject('NativeTrace.py')
 
 Source('activity.cc')
 Source('base.cc')
@@ -121,6 +114,7 @@ Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
 Source('inteltrace.cc')
+Source('nativetrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
@@ -138,10 +132,6 @@ if env['FULL_SYSTEM']:
         SimObject('LegionTrace.py')
         Source('legiontrace.cc')
 
-if env['TARGET_ISA'] == 'x86':
-    SimObject('NativeTrace.py')
-    Source('nativetrace.cc')
-
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
     TraceFlag('Checker')
@@ -164,6 +154,7 @@ TraceFlag('DynInst')
 TraceFlag('ExecEnable')
 TraceFlag('ExecCPSeq')
 TraceFlag('ExecEffAddr')
+TraceFlag('ExecFaulting', 'Trace faulting instructions')
 TraceFlag('ExecFetchSeq')
 TraceFlag('ExecOpClass')
 TraceFlag('ExecRegDelta')
@@ -180,6 +171,6 @@ TraceFlag('PCEvent')
 TraceFlag('Quiesce')
 
 CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
-    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro' ])
+    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
 CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
-    'ExecEffAddr', 'ExecResult', 'ExecMicro' ])
+    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])