X86: Make the timing simple CPU handle variable length instructions.

[gem5.git] / src / cpu / SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 1c2278f6f3291e67aa374e35d6972c103c730649..750e1ee4c46e8e3978ba390c1066767d64caa00b 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -71,8 +71,9 @@ temp_cpu_list = env['CPU_MODELS'][:]
 
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
+    SimObject('CheckerCPU.py')
 
-# Generate header.  
+# Generate header.
 def gen_cpu_exec_signatures(target, source, env):
     f = open(str(target[0]), 'w')
     print >> f, '''
@@ -103,24 +104,41 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
 # and one of these are not being used.
 CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 
+SimObject('BaseCPU.py')
+SimObject('FuncUnit.py')
+SimObject('ExeTracer.py')
+SimObject('IntelTrace.py')
+
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
-Source('op_class.cc')
+Source('inteltrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
 Source('simple_thread.cc')
+Source('thread_context.cc')
 Source('thread_state.cc')
 
 if env['FULL_SYSTEM']:
+    SimObject('IntrControl.py')
+
     Source('intr_control.cc')
     Source('profile.cc')
 
+    if env['TARGET_ISA'] == 'sparc':
+        SimObject('LegionTrace.py')
+        Source('legiontrace.cc')
+
+if env['TARGET_ISA'] == 'x86':
+    SimObject('NativeTrace.py')
+    Source('nativetrace.cc')
+
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
+    TraceFlag('Checker')
     checker_supports = False
     for i in CheckerSupportedCPUList:
         if i in env['CPU_MODELS']:
@@ -131,3 +149,31 @@ if env['USE_CHECKER']:
             print i,
         print ", please set USE_CHECKER=False or use one of those CPU models"
         Exit(1)
+# Workaround for bug in SCons version > 0.97d20071212
+# Scons bug id: 2006 M5 Bug id: 308
+else:
+    Dir('checker')
+
+TraceFlag('Activity')
+TraceFlag('Commit')
+TraceFlag('Context')
+TraceFlag('Decode')
+TraceFlag('DynInst')
+TraceFlag('ExecEnable')
+TraceFlag('ExecCPSeq')
+TraceFlag('ExecEffAddr')
+TraceFlag('ExecFetchSeq')
+TraceFlag('ExecOpClass')
+TraceFlag('ExecRegDelta')
+TraceFlag('ExecResult')
+TraceFlag('ExecSpeculative')
+TraceFlag('ExecSymbol')
+TraceFlag('ExecThread')
+TraceFlag('ExecTicks')
+TraceFlag('Fetch')
+TraceFlag('IntrControl')
+TraceFlag('PCEvent')
+TraceFlag('Quiesce')
+
+CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
+    'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])