X86: Make the timing simple CPU handle variable length instructions.

[gem5.git] / src / cpu / SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 6b43c6c1617312784007ba8583949bae9d7f26c8..750e1ee4c46e8e3978ba390c1066767d64caa00b 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -71,6 +71,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
 
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
+    SimObject('CheckerCPU.py')
 
 # Generate header.
 def gen_cpu_exec_signatures(target, source, env):
@@ -118,6 +119,7 @@ Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
 Source('simple_thread.cc')
+Source('thread_context.cc')
 Source('thread_state.cc')
 
 if env['FULL_SYSTEM']:
@@ -147,9 +149,14 @@ if env['USE_CHECKER']:
             print i,
         print ", please set USE_CHECKER=False or use one of those CPU models"
         Exit(1)
+# Workaround for bug in SCons version > 0.97d20071212
+# Scons bug id: 2006 M5 Bug id: 308
+else:
+    Dir('checker')
 
 TraceFlag('Activity')
 TraceFlag('Commit')
+TraceFlag('Context')
 TraceFlag('Decode')
 TraceFlag('DynInst')
 TraceFlag('ExecEnable')