Turn the instruction tracing code into pluggable sim objects.

[gem5.git] / src / cpu / SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index cce13a072aea8cff15cd332f6529736e17e5b6f7..b686c0d95a9c9c844f9d0085b3c15a5feed42d28 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -72,7 +72,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
 
-# Generate header.  
+# Generate header.
 def gen_cpu_exec_signatures(target, source, env):
     f = open(str(target[0]), 'w')
     print >> f, '''
@@ -105,13 +105,15 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 
 SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
+SimObject('ExeTracer.py')
+SimObject('IntelTrace.py')
 
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
-Source('op_class.cc')
+Source('inteltrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
@@ -124,6 +126,14 @@ if env['FULL_SYSTEM']:
     Source('intr_control.cc')
     Source('profile.cc')
 
+    if env['TARGET_ISA'] == 'sparc':
+        SimObject('LegionTrace.py')
+        Source('legiontrace.cc')
+
+if env['TARGET_ISA'] == 'x86':
+    SimObject('NativeTrace.py')
+    Source('nativetrace.cc')
+
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
     checker_supports = False