inorder: add insts to cpu event

[gem5.git] / src / cpu / SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index adf47fa4dd2d05b7e46d4836e177a81f7ba350a7..b89a589c62fabdcd111cc9f4d641ed5e23e1a870 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -48,15 +48,19 @@ execfile(models_db.srcnode().abspath)
 
 # Template for execute() signature.
 exec_sig_template = '''
-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
+virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
+virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
 { panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
-virtual Fault completeAcc(Packet *pkt, %s *xc,
+virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
                           Trace::InstRecord *traceData) const
 { panic("completeAcc not defined!"); M5_DUMMY_RETURN };
 '''
 
 mem_ini_sig_template = '''
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
 virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
 '''
 
@@ -71,6 +75,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
 
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
+    SimObject('CheckerCPU.py')
 
 # Generate header.
 def gen_cpu_exec_signatures(target, source, env):
@@ -81,7 +86,7 @@ def gen_cpu_exec_signatures(target, source, env):
 '''
     for cpu in temp_cpu_list:
         xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
-        print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
+        print >> f, exec_sig_template % { 'type' : xc_type }
     print >> f, '''
 #endif  // __CPU_STATIC_INST_EXEC_SIGS_HH__
 '''
@@ -105,16 +110,22 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
 
 SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
+SimObject('ExeTracer.py')
+SimObject('IntelTrace.py')
+SimObject('NativeTrace.py')
 
 Source('activity.cc')
 Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
+Source('inteltrace.cc')
+Source('nativetrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
 Source('simple_thread.cc')
+Source('thread_context.cc')
 Source('thread_state.cc')
 
 if env['FULL_SYSTEM']:
@@ -123,8 +134,13 @@ if env['FULL_SYSTEM']:
     Source('intr_control.cc')
     Source('profile.cc')
 
+    if env['TARGET_ISA'] == 'sparc':
+        SimObject('LegionTrace.py')
+        Source('legiontrace.cc')
+
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
+    TraceFlag('Checker')
     checker_supports = False
     for i in CheckerSupportedCPUList:
         if i in env['CPU_MODELS']:
@@ -135,3 +151,32 @@ if env['USE_CHECKER']:
             print i,
         print ", please set USE_CHECKER=False or use one of those CPU models"
         Exit(1)
+
+TraceFlag('Activity')
+TraceFlag('Commit')
+TraceFlag('Context')
+TraceFlag('Decode')
+TraceFlag('DynInst')
+TraceFlag('ExecEnable')
+TraceFlag('ExecCPSeq')
+TraceFlag('ExecEffAddr')
+TraceFlag('ExecFaulting', 'Trace faulting instructions')
+TraceFlag('ExecFetchSeq')
+TraceFlag('ExecOpClass')
+TraceFlag('ExecRegDelta')
+TraceFlag('ExecResult')
+TraceFlag('ExecSpeculative')
+TraceFlag('ExecSymbol')
+TraceFlag('ExecThread')
+TraceFlag('ExecTicks')
+TraceFlag('ExecMicro')
+TraceFlag('ExecMacro')
+TraceFlag('Fetch')
+TraceFlag('IntrControl')
+TraceFlag('PCEvent')
+TraceFlag('Quiesce')
+
+CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
+    'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
+CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
+    'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting' ])