Import('*')
+if env['TARGET_ISA'] == 'no':
+ Return()
+
#################################################################
#
# Generate StaticInst execute() method signatures.
#
#################################################################
-# CPU model-specific data is contained in cpu_models.py
-# Convert to SCons File node to get path handling
-models_db = File('cpu_models.py')
-# slurp in contents of file
-execfile(models_db.srcnode().abspath)
-
# Template for execute() signature.
exec_sig_template = '''
-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
+virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
+virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
-virtual Fault completeAcc(Packet *pkt, %s *xc,
+virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
+virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
+{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
'''
# it's enabled. This isn't used for anything else other than StaticInst
# headers.
temp_cpu_list = env['CPU_MODELS'][:]
-
-if env['USE_CHECKER']:
- temp_cpu_list.append('CheckerCPU')
+temp_cpu_list.append('CheckerCPU')
+SimObject('CheckerCPU.py')
# Generate header.
def gen_cpu_exec_signatures(target, source, env):
'''
for cpu in temp_cpu_list:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
- print >> f, exec_sig_template % (xc_type, xc_type, xc_type)
+ print >> f, exec_sig_template % { 'type' : xc_type }
print >> f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
# Generate string that gets printed when header is rebuilt
def gen_sigs_string(target, source, env):
- return "Generating static_inst_exec_sigs.hh: " \
+ return " [GENERATE] static_inst_exec_sigs.hh: " \
+ ', '.join(temp_cpu_list)
# Add command to generate header to environment.
-env.Command('static_inst_exec_sigs.hh', models_db,
+env.Command('static_inst_exec_sigs.hh', (),
Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = temp_cpu_list))
-env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
-# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
-# and one of these are not being used.
-CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
-
SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
+SimObject('IntrControl.py')
+SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
+Source('intr_control.cc')
+Source('nativetrace.cc')
Source('pc_event.cc')
+Source('profile.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
Source('simple_thread.cc')
Source('thread_context.cc')
Source('thread_state.cc')
-if env['FULL_SYSTEM']:
- SimObject('IntrControl.py')
-
- Source('intr_control.cc')
- Source('profile.cc')
-
- if env['TARGET_ISA'] == 'sparc':
- SimObject('LegionTrace.py')
- Source('legiontrace.cc')
-
-if env['TARGET_ISA'] == 'x86':
- SimObject('NativeTrace.py')
- Source('nativetrace.cc')
-
-if env['USE_CHECKER']:
- Source('checker/cpu.cc')
- TraceFlag('Checker')
- checker_supports = False
- for i in CheckerSupportedCPUList:
- if i in env['CPU_MODELS']:
- checker_supports = True
- if not checker_supports:
- print "Checker only supports CPU models",
- for i in CheckerSupportedCPUList:
- print i,
- print ", please set USE_CHECKER=False or use one of those CPU models"
- Exit(1)
-
-TraceFlag('Activity')
-TraceFlag('Commit')
-TraceFlag('Context')
-TraceFlag('Decode')
-TraceFlag('DynInst')
-TraceFlag('ExecEnable')
-TraceFlag('ExecCPSeq')
-TraceFlag('ExecEffAddr')
-TraceFlag('ExecFetchSeq')
-TraceFlag('ExecOpClass')
-TraceFlag('ExecRegDelta')
-TraceFlag('ExecResult')
-TraceFlag('ExecSpeculative')
-TraceFlag('ExecSymbol')
-TraceFlag('ExecThread')
-TraceFlag('ExecTicks')
-TraceFlag('Fetch')
-TraceFlag('IntrControl')
-TraceFlag('PCEvent')
-TraceFlag('Quiesce')
-
+if env['TARGET_ISA'] == 'sparc':
+ SimObject('LegionTrace.py')
+ Source('legiontrace.cc')
+
+SimObject('DummyChecker.py')
+Source('checker/cpu.cc')
+Source('dummy_checker_builder.cc')
+DebugFlag('Checker')
+
+DebugFlag('Activity')
+DebugFlag('Commit')
+DebugFlag('Context')
+DebugFlag('Decode')
+DebugFlag('DynInst')
+DebugFlag('ExecEnable')
+DebugFlag('ExecCPSeq')
+DebugFlag('ExecEffAddr')
+DebugFlag('ExecFaulting', 'Trace faulting instructions')
+DebugFlag('ExecFetchSeq')
+DebugFlag('ExecOpClass')
+DebugFlag('ExecRegDelta')
+DebugFlag('ExecResult')
+DebugFlag('ExecSpeculative')
+DebugFlag('ExecSymbol')
+DebugFlag('ExecThread')
+DebugFlag('ExecTicks')
+DebugFlag('ExecMicro')
+DebugFlag('ExecMacro')
+DebugFlag('ExecUser')
+DebugFlag('ExecKernel')
+DebugFlag('ExecAsid')
+DebugFlag('Fetch')
+DebugFlag('IntrControl')
+DebugFlag('O3PipeView')
+DebugFlag('PCEvent')
+DebugFlag('Quiesce')
+
+CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
+ 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
+ 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
+ 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
+ 'ExecAsid' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
- 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ])
+ 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
+ 'ExecUser', 'ExecKernel' ])
+CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
+ 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
+ 'ExecUser', 'ExecKernel' ])
projects / gem5.git / blobdiff