+# Copyright (c) 2020 ARM Limited
# Copyright (c) 2003-2005 The Regents of The University of Michigan
# Copyright (c) 2013 Advanced Micro Devices, Inc.
# All rights reserved.
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
from m5.params import *
'IsInteger', # References integer regs.
'IsFloating', # References FP regs.
'IsCC', # References CC regs.
+ 'IsVector', # References Vector regs.
+ 'IsVectorElem', # References Vector reg elems.
'IsMemRef', # References memory (load, store, or prefetch)
'IsLoad', # Reads from memory (load or prefetch).
'IsStore', # Writes to memory.
+ 'IsAtomic', # Does atomic RMW to memory.
'IsStoreConditional', # Store conditional instruction.
'IsIndexed', # Accesses memory with an indexed address
# computation
'IsCall', # Subroutine call.
'IsReturn', # Subroutine return.
- 'IsCondDelaySlot', # Conditional Delay-Slot Instruction
-
- 'IsThreadSync', # Thread synchronization operation.
-
'IsSerializing', # Serializes pipeline: won't execute until all
# older instructions have committed.
'IsSerializeBefore',
'IsMemBarrier', # Is a memory barrier
'IsWriteBarrier', # Is a write barrier
'IsReadBarrier', # Is a read barrier
- 'IsERET', # <- Causes the IFU to stall (MIPS ISA)
'IsNonSpeculative', # Should not be executed speculatively
'IsQuiesce', # Is a quiesce instruction
'IsMicroBranch', # This microop branches within the microcode for
# a macroop
'IsDspOp',
- 'IsSquashAfter' # Squash all uncommitted state after executed
+ 'IsSquashAfter', # Squash all uncommitted state after executed
+ # hardware transactional memory
+ 'IsHtmStart', # Starts a HTM transaction
+ 'IsHtmStop', # Stops (commits) a HTM transaction
+ 'IsHtmCancel' # Explicitely aborts a HTM transaction
]