X86: Implement the sysret instruction in long mode.

[gem5.git] / src / cpu / base.cc

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 06fcebad89ca0d919ecf2ad1801fad793970ee58..0ef206d901a8766b85a14d030c2433976c6c2994 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -344,8 +344,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
         assert(newTC->threadId() == oldTC->threadId());
         system->replaceThreadContext(newTC, newTC->contextId());
 
-        if (DTRACE(Context))
+        /* This code no longer works since the zero register (e.g.,
+         * r31 on Alpha) doesn't necessarily contain zero at this
+         * point.
+           if (DTRACE(Context))
             ThreadContext::compare(oldTC, newTC);
+        */
     }
 
 #if FULL_SYSTEM