/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "base/misc.hh"
#include "base/output.hh"
#include "base/trace.hh"
-#include "config/use_checker.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
// Hack
#include "sim/stat_control.hh"
void
CPUProgressEvent::process()
{
- Counter temp = cpu->totalInstructions();
+ Counter temp = cpu->totalOps();
#ifndef NDEBUG
- double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
+ double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
"%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
return "CPU Progress";
}
-BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
- interrupts(p->interrupts),
- numThreads(p->numThreads), system(p->system),
- phase(p->phase)
+BaseCPU::BaseCPU(Params *p, bool is_checker)
+ : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
+ _instMasterId(p->system->getMasterId(name() + ".inst")),
+ _dataMasterId(p->system->getMasterId(name() + ".data")),
+ _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
+ interrupts(p->interrupts), profileEvent(NULL),
+ numThreads(p->numThreads), system(p->system)
{
-// currentTick = curTick();
-
// if Python did not provide a valid ID, do it here
if (_cpuId == -1 ) {
_cpuId = cpuList.size();
schedule(event, p->function_trace_start);
}
}
- // Check if CPU model has interrupts connected. The CheckerCPU
- // cannot take interrupts directly for example.
- if (interrupts)
- interrupts->setCPU(this);
+
+ // The interrupts should always be present unless this CPU is
+ // switched in later or in case it is a checker CPU
+ if (!params()->defer_registration && !is_checker) {
+ if (interrupts) {
+ interrupts->setCPU(this);
+ } else {
+ fatal("CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+ }
if (FullSystem) {
- profileEvent = NULL;
if (params()->profile)
profileEvent = new ProfileEvent(this, params()->profile);
}
tracer = params()->tracer;
+
+ if (params()->isa.size() != numThreads) {
+ fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
+ "of threads (%i).\n", params()->isa.size(), numThreads);
+ }
}
void
BaseCPU::~BaseCPU()
{
+ delete profileEvent;
+ delete[] comLoadEventQueue;
+ delete[] comInstEventQueue;
}
void
}
if (params()->progress_interval) {
- Tick num_ticks = ticks(params()->progress_interval);
-
- new CPUProgressEvent(this, num_ticks);
+ new CPUProgressEvent(this, params()->progress_interval);
}
}
threadContexts[0]->regStats(name());
}
-Tick
-BaseCPU::nextCycle()
+BaseMasterPort &
+BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
- Tick next_tick = curTick() - phase + clock - 1;
- next_tick -= (next_tick % clock);
- next_tick += phase;
- return next_tick;
-}
-
-Tick
-BaseCPU::nextCycle(Tick begin_tick)
-{
- Tick next_tick = begin_tick;
- if (next_tick % clock != 0)
- next_tick = next_tick - (next_tick % clock) + clock;
- next_tick += phase;
-
- assert(next_tick >= curTick());
- return next_tick;
+ // Get the right port based on name. This applies to all the
+ // subclasses of the base CPU and relies on their implementation
+ // of getDataPort and getInstPort. In all cases there methods
+ // return a CpuPort pointer.
+ if (if_name == "dcache_port")
+ return getDataPort();
+ else if (if_name == "icache_port")
+ return getInstPort();
+ else
+ return MemObject::getMasterPort(if_name, idx);
}
void
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
- Port *ic = getPort("icache_port");
- Port *dc = getPort("dcache_port");
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
+ _pid = oldCPU->getPid();
+ _taskId = oldCPU->taskId();
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext::compare(oldTC, newTC);
*/
- Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
- old_itb_port = oldTC->getITBPtr()->getPort();
- old_dtb_port = oldTC->getDTBPtr()->getPort();
- new_itb_port = newTC->getITBPtr()->getPort();
- new_dtb_port = newTC->getDTBPtr()->getPort();
+ BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
+ BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
- if (new_itb_port && !new_itb_port->isConnected()) {
+ if (new_itb_port) {
+ assert(!new_itb_port->isConnected());
assert(old_itb_port);
- Port *peer = old_itb_port->getPeer();;
- new_itb_port->setPeer(peer);
- peer->setPeer(new_itb_port);
+ assert(old_itb_port->isConnected());
+ BaseSlavePort &slavePort = old_itb_port->getSlavePort();
+ old_itb_port->unbind();
+ new_itb_port->bind(slavePort);
}
- if (new_dtb_port && !new_dtb_port->isConnected()) {
+ if (new_dtb_port) {
+ assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
- Port *peer = old_dtb_port->getPeer();;
- new_dtb_port->setPeer(peer);
- peer->setPeer(new_dtb_port);
+ assert(old_dtb_port->isConnected());
+ BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
+ old_dtb_port->unbind();
+ new_dtb_port->bind(slavePort);
}
-#if USE_CHECKER
- Port *old_checker_itb_port, *old_checker_dtb_port;
- Port *new_checker_itb_port, *new_checker_dtb_port;
-
- CheckerCPU *oldChecker =
- dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr());
- CheckerCPU *newChecker =
- dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr());
- old_checker_itb_port = oldChecker->getITBPtr()->getPort();
- old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
- new_checker_itb_port = newChecker->getITBPtr()->getPort();
- new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
-
- // Move over any table walker ports if they exist for checker
- if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
- assert(old_checker_itb_port);
- Port *peer = old_checker_itb_port->getPeer();;
- new_checker_itb_port->setPeer(peer);
- peer->setPeer(new_checker_itb_port);
- }
- if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
- assert(old_checker_dtb_port);
- Port *peer = old_checker_dtb_port->getPeer();;
- new_checker_dtb_port->setPeer(peer);
- peer->setPeer(new_checker_dtb_port);
+ // Checker whether or not we have to transfer CheckerCPU
+ // objects over in the switch
+ CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
+ CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
+ if (oldChecker && newChecker) {
+ BaseMasterPort *old_checker_itb_port =
+ oldChecker->getITBPtr()->getMasterPort();
+ BaseMasterPort *old_checker_dtb_port =
+ oldChecker->getDTBPtr()->getMasterPort();
+ BaseMasterPort *new_checker_itb_port =
+ newChecker->getITBPtr()->getMasterPort();
+ BaseMasterPort *new_checker_dtb_port =
+ newChecker->getDTBPtr()->getMasterPort();
+
+ // Move over any table walker ports if they exist for checker
+ if (new_checker_itb_port) {
+ assert(!new_checker_itb_port->isConnected());
+ assert(old_checker_itb_port);
+ assert(old_checker_itb_port->isConnected());
+ BaseSlavePort &slavePort =
+ old_checker_itb_port->getSlavePort();
+ old_checker_itb_port->unbind();
+ new_checker_itb_port->bind(slavePort);
+ }
+ if (new_checker_dtb_port) {
+ assert(!new_checker_dtb_port->isConnected());
+ assert(old_checker_dtb_port);
+ assert(old_checker_dtb_port->isConnected());
+ BaseSlavePort &slavePort =
+ old_checker_dtb_port->getSlavePort();
+ old_checker_dtb_port->unbind();
+ new_checker_dtb_port->bind(slavePort);
+ }
}
-#endif
-
}
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
if (FullSystem) {
for (ThreadID i = 0; i < size; ++i)
schedule(profileEvent, curTick());
}
- // Connect new CPU to old CPU's memory only if new CPU isn't
- // connected to anything. Also connect old CPU's memory to new
- // CPU.
- if (!ic->isConnected()) {
- Port *peer = oldCPU->getPort("icache_port")->getPeer();
- ic->setPeer(peer);
- peer->setPeer(ic);
- }
-
- if (!dc->isConnected()) {
- Port *peer = oldCPU->getPort("dcache_port")->getPeer();
- dc->setPeer(peer);
- peer->setPeer(dc);
- }
+ // All CPUs have an instruction and a data port, and the new CPU's
+ // ports are dangling while the old CPU has its ports connected
+ // already. Unbind the old CPU and then bind the ports of the one
+ // we are switching to.
+ assert(!getInstPort().isConnected());
+ assert(oldCPU->getInstPort().isConnected());
+ BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ oldCPU->getInstPort().unbind();
+ getInstPort().bind(inst_peer_port);
+
+ assert(!getDataPort().isConnected());
+ assert(oldCPU->getDataPort().isConnected());
+ BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ oldCPU->getDataPort().unbind();
+ getDataPort().bind(data_peer_port);
}
BaseCPU::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(instCnt);
+
+ /* Unlike _pid, _taskId is not serialized, as they are dynamically
+ * assigned unique ids that are only meaningful for the duration of
+ * a specific run. We will need to serialize the entire taskMap in
+ * system. */
+ SERIALIZE_SCALAR(_pid);
+
interrupts->serialize(os);
}
BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
{
UNSERIALIZE_SCALAR(instCnt);
+ UNSERIALIZE_SCALAR(_pid);
interrupts->unserialize(cp, section);
}
}
bool
-BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
+BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
{
- panic("BaseCPU doesn't expect recvTiming callback!");
+ panic("BaseCPU doesn't expect recvTiming!\n");
return true;
}
void
BaseCPU::CpuPort::recvRetry()
{
- panic("BaseCPU doesn't expect recvRetry callback!");
-}
-
-Tick
-BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
-{
- panic("BaseCPU doesn't expect recvAtomic callback!");
- return curTick();
-}
-
-void
-BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
-{
- // No internal storage to update (in the general case). In the
- // long term this should never be called, but that assumed a split
- // into master/slave and request/response.
+ panic("BaseCPU doesn't expect recvRetry!\n");
}
void
-BaseCPU::CpuPort::recvRangeChange()
+BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
{
+ // No internal storage to update (in the general case). A CPU with
+ // internal storage, e.g. an LSQ that should be part of the
+ // coherent memory has to check against stored data.
}
projects / gem5.git / blobdiff