/*
+ * Copyright (c) 2011-2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
* All rights reserved.
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
void
CPUProgressEvent::process()
{
- Counter temp = cpu->totalInstructions();
+ Counter temp = cpu->totalOps();
#ifndef NDEBUG
- double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
+ double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
"%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
return "CPU Progress";
}
-#if FULL_SYSTEM
-BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
- interrupts(p->interrupts),
- numThreads(p->numThreads), system(p->system),
- phase(p->phase)
-#else
-BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
- numThreads(p->numThreads), system(p->system),
- phase(p->phase)
-#endif
+BaseCPU::BaseCPU(Params *p, bool is_checker)
+ : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
+ _instMasterId(p->system->getMasterId(name() + ".inst")),
+ _dataMasterId(p->system->getMasterId(name() + ".data")),
+ _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
+ _switchedOut(p->switched_out),
+ interrupts(p->interrupts), profileEvent(NULL),
+ numThreads(p->numThreads), system(p->system)
{
-// currentTick = curTick();
-
// if Python did not provide a valid ID, do it here
if (_cpuId == -1 ) {
_cpuId = cpuList.size();
functionTracingEnabled = false;
if (p->function_trace) {
- functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
+ const string fname = csprintf("ftrace.%s", name());
+ functionTraceStream = simout.find(fname);
+ if (!functionTraceStream)
+ functionTraceStream = simout.create(fname);
+
currentFunctionStart = currentFunctionEnd = 0;
functionEntryTick = p->function_trace_start;
schedule(event, p->function_trace_start);
}
}
-#if FULL_SYSTEM
- interrupts->setCPU(this);
- profileEvent = NULL;
- if (params()->profile)
- profileEvent = new ProfileEvent(this, params()->profile);
-#endif
+ // The interrupts should always be present unless this CPU is
+ // switched in later or in case it is a checker CPU
+ if (!params()->switched_out && !is_checker) {
+ if (interrupts) {
+ interrupts->setCPU(this);
+ } else {
+ fatal("CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+ }
+
+ if (FullSystem) {
+ if (params()->profile)
+ profileEvent = new ProfileEvent(this, params()->profile);
+ }
tracer = params()->tracer;
+
+ if (params()->isa.size() != numThreads) {
+ fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
+ "of threads (%i).\n", params()->isa.size(), numThreads);
+ }
}
void
BaseCPU::~BaseCPU()
{
+ delete profileEvent;
+ delete[] comLoadEventQueue;
+ delete[] comInstEventQueue;
}
void
BaseCPU::init()
{
- if (!params()->defer_registration)
+ if (!params()->switched_out)
registerThreadContexts();
}
void
BaseCPU::startup()
{
-#if FULL_SYSTEM
- if (!params()->defer_registration && profileEvent)
- schedule(profileEvent, curTick());
-#endif
+ if (FullSystem) {
+ if (!params()->switched_out && profileEvent)
+ schedule(profileEvent, curTick());
+ }
if (params()->progress_interval) {
- Tick num_ticks = ticks(params()->progress_interval);
-
- new CPUProgressEvent(this, num_ticks);
+ new CPUProgressEvent(this, params()->progress_interval);
}
}
}
} else if (size == 1)
threadContexts[0]->regStats(name());
-
-#if FULL_SYSTEM
-#endif
-}
-
-Tick
-BaseCPU::nextCycle()
-{
- Tick next_tick = curTick() - phase + clock - 1;
- next_tick -= (next_tick % clock);
- next_tick += phase;
- return next_tick;
}
-Tick
-BaseCPU::nextCycle(Tick begin_tick)
+BaseMasterPort &
+BaseCPU::getMasterPort(const string &if_name, PortID idx)
{
- Tick next_tick = begin_tick;
- if (next_tick % clock != 0)
- next_tick = next_tick - (next_tick % clock) + clock;
- next_tick += phase;
-
- assert(next_tick >= curTick());
- return next_tick;
+ // Get the right port based on name. This applies to all the
+ // subclasses of the base CPU and relies on their implementation
+ // of getDataPort and getInstPort. In all cases there methods
+ // return a CpuPort pointer.
+ if (if_name == "dcache_port")
+ return getDataPort();
+ else if (if_name == "icache_port")
+ return getInstPort();
+ else
+ return MemObject::getMasterPort(if_name, idx);
}
void
tc->setContextId(system->registerThreadContext(tc, _cpuId));
else
tc->setContextId(system->registerThreadContext(tc));
-#if !FULL_SYSTEM
- tc->getProcessPtr()->assignThreadContext(tc->contextId());
-#endif
+
+ if (!FullSystem)
+ tc->getProcessPtr()->assignThreadContext(tc->contextId());
}
}
void
BaseCPU::switchOut()
{
-// panic("This CPU doesn't support sampling!");
-#if FULL_SYSTEM
+ assert(!_switchedOut);
+ _switchedOut = true;
if (profileEvent && profileEvent->scheduled())
deschedule(profileEvent);
-#endif
+
+ // Flush all TLBs in the CPU to avoid having stale translations if
+ // it gets switched in later.
+ flushTLBs();
}
void
-BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
+BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
-
- _cpuId = oldCPU->cpuId();
+ assert(_cpuId == oldCPU->cpuId());
+ assert(_switchedOut);
+ assert(oldCPU != this);
+ _pid = oldCPU->getPid();
+ _taskId = oldCPU->taskId();
+ _switchedOut = false;
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext::compare(oldTC, newTC);
*/
- Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
- old_itb_port = oldTC->getITBPtr()->getPort();
- old_dtb_port = oldTC->getDTBPtr()->getPort();
- new_itb_port = newTC->getITBPtr()->getPort();
- new_dtb_port = newTC->getDTBPtr()->getPort();
+ BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
+ BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
+ BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
// Move over any table walker ports if they exist
- if (new_itb_port && !new_itb_port->isConnected()) {
+ if (new_itb_port) {
+ assert(!new_itb_port->isConnected());
assert(old_itb_port);
- Port *peer = old_itb_port->getPeer();;
- new_itb_port->setPeer(peer);
- peer->setPeer(new_itb_port);
+ assert(old_itb_port->isConnected());
+ BaseSlavePort &slavePort = old_itb_port->getSlavePort();
+ old_itb_port->unbind();
+ new_itb_port->bind(slavePort);
}
- if (new_dtb_port && !new_dtb_port->isConnected()) {
+ if (new_dtb_port) {
+ assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
- Port *peer = old_dtb_port->getPeer();;
- new_dtb_port->setPeer(peer);
- peer->setPeer(new_dtb_port);
+ assert(old_dtb_port->isConnected());
+ BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
+ old_dtb_port->unbind();
+ new_dtb_port->bind(slavePort);
+ }
+
+ // Checker whether or not we have to transfer CheckerCPU
+ // objects over in the switch
+ CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
+ CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
+ if (oldChecker && newChecker) {
+ BaseMasterPort *old_checker_itb_port =
+ oldChecker->getITBPtr()->getMasterPort();
+ BaseMasterPort *old_checker_dtb_port =
+ oldChecker->getDTBPtr()->getMasterPort();
+ BaseMasterPort *new_checker_itb_port =
+ newChecker->getITBPtr()->getMasterPort();
+ BaseMasterPort *new_checker_dtb_port =
+ newChecker->getDTBPtr()->getMasterPort();
+
+ // Move over any table walker ports if they exist for checker
+ if (new_checker_itb_port) {
+ assert(!new_checker_itb_port->isConnected());
+ assert(old_checker_itb_port);
+ assert(old_checker_itb_port->isConnected());
+ BaseSlavePort &slavePort =
+ old_checker_itb_port->getSlavePort();
+ old_checker_itb_port->unbind();
+ new_checker_itb_port->bind(slavePort);
+ }
+ if (new_checker_dtb_port) {
+ assert(!new_checker_dtb_port->isConnected());
+ assert(old_checker_dtb_port);
+ assert(old_checker_dtb_port->isConnected());
+ BaseSlavePort &slavePort =
+ old_checker_dtb_port->getSlavePort();
+ old_checker_dtb_port->unbind();
+ new_checker_dtb_port->bind(slavePort);
+ }
}
}
-#if FULL_SYSTEM
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
+ oldCPU->interrupts = NULL;
- for (ThreadID i = 0; i < size; ++i)
- threadContexts[i]->profileClear();
-
- if (profileEvent)
- schedule(profileEvent, curTick());
-#endif
+ if (FullSystem) {
+ for (ThreadID i = 0; i < size; ++i)
+ threadContexts[i]->profileClear();
- // Connect new CPU to old CPU's memory only if new CPU isn't
- // connected to anything. Also connect old CPU's memory to new
- // CPU.
- if (!ic->isConnected()) {
- Port *peer = oldCPU->getPort("icache_port")->getPeer();
- ic->setPeer(peer);
- peer->setPeer(ic);
+ if (profileEvent)
+ schedule(profileEvent, curTick());
}
- if (!dc->isConnected()) {
- Port *peer = oldCPU->getPort("dcache_port")->getPeer();
- dc->setPeer(peer);
- peer->setPeer(dc);
+ // All CPUs have an instruction and a data port, and the new CPU's
+ // ports are dangling while the old CPU has its ports connected
+ // already. Unbind the old CPU and then bind the ports of the one
+ // we are switching to.
+ assert(!getInstPort().isConnected());
+ assert(oldCPU->getInstPort().isConnected());
+ BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ oldCPU->getInstPort().unbind();
+ getInstPort().bind(inst_peer_port);
+
+ assert(!getDataPort().isConnected());
+ assert(oldCPU->getDataPort().isConnected());
+ BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ oldCPU->getDataPort().unbind();
+ getDataPort().bind(data_peer_port);
+}
+
+void
+BaseCPU::flushTLBs()
+{
+ for (ThreadID i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext &tc(*threadContexts[i]);
+ CheckerCPU *checker(tc.getCheckerCpuPtr());
+
+ tc.getITBPtr()->flushAll();
+ tc.getDTBPtr()->flushAll();
+ if (checker) {
+ checker->getITBPtr()->flushAll();
+ checker->getDTBPtr()->flushAll();
+ }
}
}
-#if FULL_SYSTEM
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
: cpu(_cpu), interval(_interval)
{ }
BaseCPU::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(instCnt);
- interrupts->serialize(os);
+
+ if (!_switchedOut) {
+ /* Unlike _pid, _taskId is not serialized, as they are dynamically
+ * assigned unique ids that are only meaningful for the duration of
+ * a specific run. We will need to serialize the entire taskMap in
+ * system. */
+ SERIALIZE_SCALAR(_pid);
+
+ interrupts->serialize(os);
+
+ // Serialize the threads, this is done by the CPU implementation.
+ for (ThreadID i = 0; i < numThreads; ++i) {
+ nameOut(os, csprintf("%s.xc.%i", name(), i));
+ serializeThread(os, i);
+ }
+ }
}
void
BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
{
UNSERIALIZE_SCALAR(instCnt);
- interrupts->unserialize(cp, section);
-}
-#endif // FULL_SYSTEM
+ if (!_switchedOut) {
+ UNSERIALIZE_SCALAR(_pid);
+ interrupts->unserialize(cp, section);
+
+ // Unserialize the threads, this is done by the CPU implementation.
+ for (ThreadID i = 0; i < numThreads; ++i)
+ unserializeThread(cp, csprintf("%s.xc.%i", section, i), i);
+ }
+}
void
BaseCPU::traceFunctionsInternal(Addr pc)
functionEntryTick = curTick();
}
}
+
+bool
+BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
+{
+ panic("BaseCPU doesn't expect recvTiming!\n");
+ return true;
+}
+
+void
+BaseCPU::CpuPort::recvRetry()
+{
+ panic("BaseCPU doesn't expect recvRetry!\n");
+}
+
+void
+BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
+{
+ // No internal storage to update (in the general case). A CPU with
+ // internal storage, e.g. an LSQ that should be part of the
+ // coherent memory has to check against stored data.
+}
projects / gem5.git / blobdiff