base,cpu,sim: Stop including arch/vtophys.hh when not using vtophys.

[gem5.git] / src / cpu / base.cc

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 80726ac2b1e24881605c33bfddf12a1fd67be1e3..c0788db96e4cefe44d400cf17da0f9605d4fb9ae 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -39,10 +39,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- *          Nathan Binkert
- *          Rick Strong
  */
 
 #include "cpu/base.hh"
@@ -264,7 +260,7 @@ BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)
     if (secondAddr > addr)
         size = secondAddr - addr;
 
-    req->setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
+    req->setVirt(addr, size, 0x0, dataMasterId(), tc->instAddr());
 
     // translate to physical address
     Fault fault = dtb->translateAtomic(req, tc, BaseTLB::Read);
@@ -318,12 +314,6 @@ BaseCPU::init()
 
         verifyMemoryMode();
     }
-
-    //These calls eventually need to be moved to initState
-    if (FullSystem && !params()->switched_out) {
-        for (auto *tc: threadContexts)
-            TheISA::initCPU(tc, tc->contextId());
-    }
 }
 
 void