syscall_emul: [patch 13/22] add system call retry capability

[gem5.git] / src / cpu / base.hh

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 2a57c01ba653de3ea17f3b2a9272179f5465126b..14dfc260bf434b2436c9a8002a51c5ad9b87e9d9 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -189,7 +189,7 @@ class BaseCPU : public MemObject
      * @return a reference to the port with the given name
      */
     BaseMasterPort &getMasterPort(const std::string &if_name,
-                                  PortID idx = InvalidPortID);
+                                  PortID idx = InvalidPortID) override;
 
     /** Get cpu task id */
     uint32_t taskId() const { return _taskId; }
@@ -220,14 +220,14 @@ class BaseCPU : public MemObject
         return interrupts[tid];
     }
 
-    virtual void wakeup() = 0;
+    virtual void wakeup(ThreadID tid) = 0;
 
     void
     postInterrupt(ThreadID tid, int int_num, int index)
     {
         interrupts[tid]->post(int_num, index);
         if (FullSystem)
-            wakeup();
+            wakeup(tid);
     }
 
     void
@@ -279,10 +279,11 @@ class BaseCPU : public MemObject
     Trace::InstTracer * getTracer() { return tracer; }
 
     /// Notify the CPU that the indicated context is now active.
-    virtual void activateContext(ThreadID thread_num) {}
+    virtual void activateContext(ThreadID thread_num);
 
     /// Notify the CPU that the indicated context is now suspended.
-    virtual void suspendContext(ThreadID thread_num) {}
+    /// Check if possible to enter a lower power state
+    virtual void suspendContext(ThreadID thread_num);
 
     /// Notify the CPU that the indicated context is now halted.
     virtual void haltContext(ThreadID thread_num) {}
@@ -296,6 +297,10 @@ class BaseCPU : public MemObject
    /// Get the number of thread contexts available
    unsigned numContexts() { return threadContexts.size(); }
 
+    /// Convert ContextID to threadID
+    ThreadID contextToThread(ContextID cid)
+    { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
+
   public:
     typedef BaseCPUParams Params;
     const Params *params() const
@@ -303,11 +308,11 @@ class BaseCPU : public MemObject
     BaseCPU(Params *params, bool is_checker = false);
     virtual ~BaseCPU();
 
-    virtual void init();
-    virtual void startup();
-    virtual void regStats();
+    void init() override;
+    void startup() override;
+    void regStats() override;
 
-    void regProbePoints() M5_ATTR_OVERRIDE;
+    void regProbePoints() override;
 
     void registerThreadContexts();
 
@@ -399,7 +404,7 @@ class BaseCPU : public MemObject
      *
      * @param os The stream to serialize to.
      */
-    void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+    void serialize(CheckpointOut &cp) const override;
 
     /**
      * Reconstruct the state of this object from a checkpoint.
@@ -412,7 +417,7 @@ class BaseCPU : public MemObject
      * @param cp The checkpoint use.
      * @param section The section name of this object.
      */
-    void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+    void unserialize(CheckpointIn &cp) override;
 
     /**
      * Serialize a single thread.
@@ -465,6 +470,15 @@ class BaseCPU : public MemObject
      */
     void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
 
+    /**
+     * Get the number of instructions executed by the specified thread
+     * on this CPU. Used by Python to control simulation.
+     *
+     * @param tid Thread monitor
+     * @return Number of instructions executed
+     */
+    uint64_t getCurrentInstCount(ThreadID tid);
+
   public:
     /**
      * @{
@@ -574,6 +588,8 @@ class BaseCPU : public MemObject
         assert(tid < numThreads);
         return &addressMonitor[tid];
     }
+
+    Cycles syscallRetryLatency;
 };
 
 #endif // THE_ISA == NULL_ISA