class ThreadContext;
class System;
-namespace TheISA
-{
- class Predecoder;
-}
-
class CPUProgressEvent : public Event
{
protected:
* both atomic and timing access is to panic and the corresponding
* subclasses have to override these methods.
*/
- class CpuPort : public Port
+ class CpuPort : public MasterPort
{
public:
* @param _name structural owner of this port
*/
CpuPort(const std::string& _name, MemObject* _owner) :
- Port(_name, _owner)
+ MasterPort(_name, _owner)
{ }
protected:
- virtual bool recvTiming(PacketPtr pkt);
-
- virtual Tick recvAtomic(PacketPtr pkt);
+ virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();
- void recvFunctional(PacketPtr pkt);
-
- void recvRangeChange();
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
};
MasterID instMasterId() { return _instMasterId; }
/**
- * Get a port on this MemObject. This method is virtual to allow
- * the subclasses of the BaseCPU to override it. All CPUs have a
- * data and instruction port, but the Atomic CPU (in its current
- * form) adds a port directly connected to the memory and has to
- * override getPort.
- *
- * This method uses getDataPort and getInstPort to resolve the two
- * ports.
+ * Get a master port on this CPU. All CPUs have a data and
+ * instruction port, and this method uses getDataPort and
+ * getInstPort of the subclasses to resolve the two ports.
*
* @param if_name the port name
* @param idx ignored index
*
- * @return a pointer to the port with the given name
+ * @return a reference to the port with the given name
*/
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
// Tick currentTick;
inline Tick frequency() const { return SimClock::Frequency / clock; }
protected:
std::vector<ThreadContext *> threadContexts;
- std::vector<TheISA::Predecoder *> predecoders;
Trace::InstTracer * tracer;