cpu: implement a bi-mode branch predictor

[gem5.git] / src / cpu / base.hh

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 321b785a241fe20e9d4cae1e4bb15370f0e99ebd..cc3f861cca93583fd66f19d7f82597204bff1b52 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -101,6 +101,13 @@ class BaseCPU : public MemObject
     // therefore no setCpuId() method is provided
     int _cpuId;
 
+    /** Each cpu will have a socket ID that corresponds to its physical location
+     * in the system. This is usually used to bucket cpu cores under single DVFS
+     * domain. This information may also be required by the OS to identify the
+     * cpu core grouping (as in the case of ARM via MPIDR register)
+     */
+    const uint32_t _socketId;
+
     /** instruction side request id that must be placed in all requests */
     MasterID _instMasterId;
 
@@ -145,6 +152,9 @@ class BaseCPU : public MemObject
     /** Reads this CPU's ID. */
     int cpuId() const { return _cpuId; }
 
+    /** Reads this CPU's Socket ID. */
+    uint32_t socketId() const { return _socketId; }
+
     /** Reads this CPU's unique data requestor ID */
     MasterID dataMasterId() { return _dataMasterId; }
     /** Reads this CPU's unique instruction requestor ID */