/*
+ * Copyright (c) 2011-2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
*
* Authors: Steve Reinhardt
* Nathan Binkert
+ * Rick Strong
*/
#ifndef __CPU_BASE_HH__
#include <vector>
+#include "arch/interrupts.hh"
#include "arch/isa_traits.hh"
#include "arch/microcode_rom.hh"
#include "base/statistics.hh"
-#include "config/full_system.hh"
+#include "config/the_isa.hh"
+#include "mem/mem_object.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/insttracer.hh"
-#include "mem/mem_object.hh"
-#if FULL_SYSTEM
-#include "arch/interrupts.hh"
-#endif
-
-class BaseCPUParams;
+struct BaseCPUParams;
class BranchPred;
class CheckerCPU;
class ThreadContext;
class System;
-class Port;
-
-namespace TheISA
-{
- class Predecoder;
-}
class CPUProgressEvent : public Event
{
protected:
- Tick interval;
+ Tick _interval;
Counter lastNumInst;
BaseCPU *cpu;
+ bool _repeatEvent;
public:
- CPUProgressEvent(BaseCPU *_cpu, Tick ival);
+ CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
void process();
+ void interval(Tick ival) { _interval = ival; }
+ Tick interval() { return _interval; }
+
+ void repeatEvent(bool repeat) { _repeatEvent = repeat; }
+
virtual const char *description() const;
};
class BaseCPU : public MemObject
{
protected:
- // CPU's clock period in terms of the number of ticks of curTime.
- Tick clock;
+
// @todo remove me after debugging with legion done
Tick instCnt;
+ // every cpu has an id, put it in the base cpu
+ // Set at initialization, only time a cpuId might change is during a
+ // takeover (which should be done from within the BaseCPU anyway,
+ // therefore no setCpuId() method is provided
+ int _cpuId;
+
+ /** instruction side request id that must be placed in all requests */
+ MasterID _instMasterId;
+
+ /** data side request id that must be placed in all requests */
+ MasterID _dataMasterId;
+
+ /** An intrenal representation of a task identifier within gem5. This is
+ * used so the CPU can add which taskId (which is an internal representation
+ * of the OS process ID) to each request so components in the memory system
+ * can track which process IDs are ultimately interacting with them
+ */
+ uint32_t _taskId;
+
+ /** The current OS process ID that is executing on this processor. This is
+ * used to generate a taskId */
+ uint32_t _pid;
+
+ /** Is the CPU switched out or active? */
+ bool _switchedOut;
+
+ /**
+ * Define a base class for the CPU ports (instruction and data)
+ * that is refined in the subclasses. This class handles the
+ * common cases, i.e. the functional accesses and the status
+ * changes and address range queries. The default behaviour for
+ * both atomic and timing access is to panic and the corresponding
+ * subclasses have to override these methods.
+ */
+ class CpuPort : public MasterPort
+ {
+ public:
+
+ /**
+ * Create a CPU port with a name and a structural owner.
+ *
+ * @param _name port name including the owner
+ * @param _name structural owner of this port
+ */
+ CpuPort(const std::string& _name, MemObject* _owner) :
+ MasterPort(_name, _owner)
+ { }
+
+ protected:
+
+ virtual bool recvTimingResp(PacketPtr pkt);
+
+ virtual void recvRetry();
+
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+
+ };
public:
-// Tick currentTick;
- inline Tick frequency() const { return Clock::Frequency / clock; }
- inline Tick ticks(int numCycles) const { return clock * numCycles; }
- inline Tick curCycle() const { return curTick / clock; }
- inline Tick tickToCycles(Tick val) const { return val / clock; }
- // @todo remove me after debugging with legion done
- Tick instCount() { return instCnt; }
- /** The next cycle the CPU should be scheduled, given a cache
- * access or quiesce event returning on this cycle. This function
- * may return curTick if the CPU should run on the current cycle.
+ /**
+ * Purely virtual method that returns a reference to the data
+ * port. All subclasses must implement this method.
+ *
+ * @return a reference to the data port
*/
- Tick nextCycle();
+ virtual CpuPort &getDataPort() = 0;
- /** The next cycle the CPU should be scheduled, given a cache
- * access or quiesce event returning on the given Tick. This
- * function may return curTick if the CPU should run on the
- * current cycle.
- * @param begin_tick The tick that the event is completing on.
+ /**
+ * Purely virtual method that returns a reference to the instruction
+ * port. All subclasses must implement this method.
+ *
+ * @return a reference to the instruction port
*/
- Tick nextCycle(Tick begin_tick);
+ virtual CpuPort &getInstPort() = 0;
+
+ /** Reads this CPU's ID. */
+ int cpuId() { return _cpuId; }
+
+ /** Reads this CPU's unique data requestor ID */
+ MasterID dataMasterId() { return _dataMasterId; }
+ /** Reads this CPU's unique instruction requestor ID */
+ MasterID instMasterId() { return _instMasterId; }
+
+ /**
+ * Get a master port on this CPU. All CPUs have a data and
+ * instruction port, and this method uses getDataPort and
+ * getInstPort of the subclasses to resolve the two ports.
+ *
+ * @param if_name the port name
+ * @param idx ignored index
+ *
+ * @return a reference to the port with the given name
+ */
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID);
+
+ /** Get cpu task id */
+ uint32_t taskId() const { return _taskId; }
+ /** Set cpu task id */
+ void taskId(uint32_t id) { _taskId = id; }
+
+ uint32_t getPid() const { return _pid; }
+ void setPid(uint32_t pid) { _pid = pid; }
+
+ inline void workItemBegin() { numWorkItemsStarted++; }
+ inline void workItemEnd() { numWorkItemsCompleted++; }
+ // @todo remove me after debugging with legion done
+ Tick instCount() { return instCnt; }
TheISA::MicrocodeRom microcodeRom;
-#if FULL_SYSTEM
protected:
TheISA::Interrupts *interrupts;
return interrupts;
}
- virtual void postInterrupt(int int_num, int index);
- virtual void clearInterrupt(int int_num, int index);
- virtual void clearInterrupts();
+ virtual void wakeup() = 0;
+
+ void
+ postInterrupt(int int_num, int index)
+ {
+ interrupts->post(int_num, index);
+ if (FullSystem)
+ wakeup();
+ }
+
+ void
+ clearInterrupt(int int_num, int index)
+ {
+ interrupts->clear(int_num, index);
+ }
+
+ void
+ clearInterrupts()
+ {
+ interrupts->clearAll();
+ }
bool
checkInterrupts(ThreadContext *tc) const
{
- return interrupts->checkInterrupts(tc);
+ return FullSystem && interrupts->checkInterrupts(tc);
}
class ProfileEvent : public Event
void process();
};
ProfileEvent *profileEvent;
-#endif
protected:
std::vector<ThreadContext *> threadContexts;
- std::vector<TheISA::Predecoder *> predecoders;
Trace::InstTracer * tracer;
public:
+ // Mask to align PCs to MachInst sized boundaries
+ static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
/// Provide access to the tracer pointer
Trace::InstTracer * getTracer() { return tracer; }
/// Notify the CPU that the indicated context is now active. The
/// delay parameter indicates the number of ticks to wait before
/// executing (typically 0 or 1).
- virtual void activateContext(int thread_num, int delay) {}
+ virtual void activateContext(ThreadID thread_num, Cycles delay) {}
/// Notify the CPU that the indicated context is now suspended.
- virtual void suspendContext(int thread_num) {}
+ virtual void suspendContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now deallocated.
- virtual void deallocateContext(int thread_num) {}
+ virtual void deallocateContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now halted.
- virtual void haltContext(int thread_num) {}
+ virtual void haltContext(ThreadID thread_num) {}
/// Given a Thread Context pointer return the thread num
int findContext(ThreadContext *tc);
typedef BaseCPUParams Params;
const Params *params() const
{ return reinterpret_cast<const Params *>(_params); }
- BaseCPU(Params *params);
+ BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
virtual void init();
virtual void startup();
virtual void regStats();
- virtual void activateWhenReady(int tid) {};
+ virtual void activateWhenReady(ThreadID tid) {};
void registerThreadContexts();
- /// Prepare for another CPU to take over execution. When it is
- /// is ready (drained pipe) it signals the sampler.
+ /**
+ * Prepare for another CPU to take over execution.
+ *
+ * When this method exits, all internal state should have been
+ * flushed. After the method returns, the simulator calls
+ * takeOverFrom() on the new CPU with this CPU as its parameter.
+ */
virtual void switchOut();
- /// Take over execution from the given CPU. Used for warm-up and
- /// sampling.
- virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
+ /**
+ * Load the state of a CPU from the previous CPU object, invoked
+ * on all new CPUs that are about to be switched in.
+ *
+ * A CPU model implementing this method is expected to initialize
+ * its state from the old CPU and connect its memory (unless they
+ * are already connected) to the memories connected to the old
+ * CPU.
+ *
+ * @param cpu CPU to initialize read state from.
+ */
+ virtual void takeOverFrom(BaseCPU *cpu);
+
+ /**
+ * Flush all TLBs in the CPU.
+ *
+ * This method is mainly used to flush stale translations when
+ * switching CPUs. It is also exported to the Python world to
+ * allow it to request a TLB flush after draining the CPU to make
+ * it easier to compare traces when debugging
+ * handover/checkpointing.
+ */
+ void flushTLBs();
+
+ /**
+ * Determine if the CPU is switched out.
+ *
+ * @return True if the CPU is switched out, false otherwise.
+ */
+ bool switchedOut() const { return _switchedOut; }
/**
* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
* This is a constant for the duration of the simulation.
*/
- int number_of_threads;
-
- TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
+ ThreadID numThreads;
/**
* Vector of per-thread instruction-based event queues. Used for
System *system;
- Tick phase;
-
-#if FULL_SYSTEM
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
*/
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-#endif
-
/**
* Return pointer to CPU's branch predictor (NULL if none).
* @return Branch predictor pointer.
*/
virtual BranchPred *getBranchPred() { return NULL; };
- virtual Counter totalInstructions() const { return 0; }
+ virtual Counter totalInsts() const = 0;
+
+ virtual Counter totalOps() const = 0;
// Function tracing
private:
void enableFunctionTrace();
void traceFunctionsInternal(Addr pc);
- protected:
+ private:
+ static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
+
+ public:
void traceFunctions(Addr pc)
{
if (functionTracingEnabled)
traceFunctionsInternal(pc);
}
- private:
- static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
-
- public:
static int numSimulatedCPUs() { return cpuList.size(); }
- static Counter numSimulatedInstructions()
+ static Counter numSimulatedInsts()
+ {
+ Counter total = 0;
+
+ int size = cpuList.size();
+ for (int i = 0; i < size; ++i)
+ total += cpuList[i]->totalInsts();
+
+ return total;
+ }
+
+ static Counter numSimulatedOps()
{
Counter total = 0;
int size = cpuList.size();
for (int i = 0; i < size; ++i)
- total += cpuList[i]->totalInstructions();
+ total += cpuList[i]->totalOps();
return total;
}
public:
// Number of CPU cycles simulated
- Stats::Scalar<> numCycles;
+ Stats::Scalar numCycles;
+ Stats::Scalar numWorkItemsStarted;
+ Stats::Scalar numWorkItemsCompleted;
};
#endif // __CPU_BASE_HH__
projects / gem5.git / blobdiff