CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

[gem5.git] / src / cpu / base.hh

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b229ddd38e14d0a0ac6440c402245e4fc04116b5..d4de55453dbd7e794294fc63b69c9ea199a9fe01 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -1,5 +1,18 @@
 /*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +40,7 @@
  *
  * Authors: Steve Reinhardt
  *          Nathan Binkert
+ *          Rick Strong
  */
 
 #ifndef __CPU_BASE_HH__
@@ -39,9 +53,9 @@
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
+#include "mem/mem_object.hh"
 #include "sim/eventq.hh"
 #include "sim/insttracer.hh"
-#include "mem/mem_object.hh"
 
 #if FULL_SYSTEM
 #include "arch/interrupts.hh"
@@ -93,27 +107,65 @@ class BaseCPU : public MemObject
     // therefore no setCpuId() method is provided
     int _cpuId;
 
+    /**
+     * Define a base class for the CPU ports (instruction and data)
+     * that is refined in the subclasses. This class handles the
+     * common cases, i.e. the functional accesses and the status
+     * changes and address range queries. The default behaviour for
+     * both atomic and timing access is to panic and the corresponding
+     * subclasses have to override these methods.
+     */
+    class CpuPort : public Port
+    {
+      public:
+
+        /**
+         * Create a CPU port with a name and a structural owner.
+         *
+         * @param _name port name including the owner
+         * @param _name structural owner of this port
+         */
+        CpuPort(const std::string& _name, MemObject* _owner) :
+            Port(_name, _owner)
+        { }
+
+      protected:
+
+        virtual bool recvTiming(PacketPtr pkt);
+
+        virtual Tick recvAtomic(PacketPtr pkt);
+
+        virtual void recvRetry();
+
+        void recvFunctional(PacketPtr pkt);
+
+        void recvRangeChange();
+
+    };
+
   public:
     /** Reads this CPU's ID. */
     int cpuId() { return _cpuId; }
 
 //    Tick currentTick;
-    inline Tick frequency() const { return Clock::Frequency / clock; }
+    inline Tick frequency() const { return SimClock::Frequency / clock; }
     inline Tick ticks(int numCycles) const { return clock * numCycles; }
-    inline Tick curCycle() const { return curTick / clock; }
+    inline Tick curCycle() const { return curTick() / clock; }
     inline Tick tickToCycles(Tick val) const { return val / clock; }
+    inline void workItemBegin() { numWorkItemsStarted++; }
+    inline void workItemEnd() { numWorkItemsCompleted++; }
     // @todo remove me after debugging with legion done
     Tick instCount() { return instCnt; }
 
     /** The next cycle the CPU should be scheduled, given a cache
      * access or quiesce event returning on this cycle.  This function
-     * may return curTick if the CPU should run on the current cycle.
+     * may return curTick() if the CPU should run on the current cycle.
      */
     Tick nextCycle();
 
     /** The next cycle the CPU should be scheduled, given a cache
      * access or quiesce event returning on the given Tick.  This
-     * function may return curTick if the CPU should run on the
+     * function may return curTick() if the CPU should run on the
      * current cycle.
      * @param begin_tick The tick that the event is completing on.
      */
@@ -180,6 +232,9 @@ class BaseCPU : public MemObject
 
   public:
 
+    // Mask to align PCs to MachInst sized boundaries
+    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
     /// Provide access to the tracer pointer
     Trace::InstTracer * getTracer() { return tracer; }
 
@@ -232,8 +287,6 @@ class BaseCPU : public MemObject
      */
     ThreadID numThreads;
 
-    TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
-
     /**
      * Vector of per-thread instruction-based event queues.  Used for
      * scheduling events based on number of instructions committed by
@@ -286,17 +339,16 @@ class BaseCPU : public MemObject
     void enableFunctionTrace();
     void traceFunctionsInternal(Addr pc);
 
-  protected:
+  private:
+    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
+
+  public:
     void traceFunctions(Addr pc)
     {
         if (functionTracingEnabled)
             traceFunctionsInternal(pc);
     }
 
-  private:
-    static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
-
-  public:
     static int numSimulatedCPUs() { return cpuList.size(); }
     static Counter numSimulatedInstructions()
     {
@@ -312,6 +364,8 @@ class BaseCPU : public MemObject
   public:
     // Number of CPU cycles simulated
     Stats::Scalar numCycles;
+    Stats::Scalar numWorkItemsStarted;
+    Stats::Scalar numWorkItemsCompleted;
 };
 
 #endif // __CPU_BASE_HH__