A possible implementation of a multiplexed bus.

[gem5.git] / src / cpu / base.hh

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 79700c117fa2c49d5810efc31281fe5c9281d0dd..e025273710e4086d6db64f8e003d0bbb81dc8e6d 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -24,6 +24,9 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ *          Nathan Binkert
  */
 
 #ifndef __CPU_BASE_HH__
@@ -33,23 +36,39 @@
 
 #include "base/statistics.hh"
 #include "config/full_system.hh"
-#include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
-#include "sim/sim_object.hh"
+#include "mem/mem_object.hh"
 #include "arch/isa_traits.hh"
 
-class System;
-namespace Kernel { class Statistics; }
 class BranchPred;
-class ExecContext;
+class CheckerCPU;
+class ThreadContext;
+class System;
+class Port;
+
+class CPUProgressEvent : public Event
+{
+  protected:
+    Tick interval;
+    Counter lastNumInst;
+    BaseCPU *cpu;
+
+  public:
+    CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
+
+    void process();
+
+    virtual const char *description();
+};
 
-class BaseCPU : public SimObject
+class BaseCPU : public MemObject
 {
   protected:
     // CPU's clock period in terms of the number of ticks of curTime.
     Tick clock;
 
   public:
+//    Tick currentTick;
     inline Tick frequency() const { return Clock::Frequency / clock; }
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
@@ -89,7 +108,7 @@ class BaseCPU : public SimObject
 #endif
 
   protected:
-    std::vector<ExecContext *> execContexts;
+    std::vector<ThreadContext *> threadContexts;
 
   public:
 
@@ -125,6 +144,8 @@ class BaseCPU : public SimObject
         int cpu_id;
         Tick profile;
 #endif
+        Tick progress_interval;
+        BaseCPU *checker;
 
         Params();
     };
@@ -140,11 +161,11 @@ class BaseCPU : public SimObject
 
     virtual void activateWhenReady(int tid) {};
 
-    void registerExecContexts();
+    void registerThreadContexts();
 
     /// Prepare for another CPU to take over execution.  When it is
     /// is ready (drained pipe) it signals the sampler.
-    virtual void switchOut(Sampler *);
+    virtual void switchOut();
 
     /// Take over execution from the given CPU.  Used for warm-up and
     /// sampling.
@@ -232,10 +253,6 @@ class BaseCPU : public SimObject
   public:
     // Number of CPU cycles simulated
     Stats::Scalar<> numCycles;
-
-#if FULL_SYSTEM
-    Kernel::Statistics *kernelStats;
-#endif
 };
 
 #endif // __CPU_BASE_HH__