#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
+#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
cpu->demapPage(vaddr, asn);
}
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
- Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size, Addr addr,
+ Request::Flags flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
void pcState(const TheISA::PCState &val) { pc = val; }
/** Read the PC of this instruction. */
- const Addr instAddr() const { return pc.instAddr(); }
+ Addr instAddr() const { return pc.instAddr(); }
/** Read the PC of the next instruction. */
- const Addr nextInstAddr() const { return pc.nextInstAddr(); }
+ Addr nextInstAddr() const { return pc.nextInstAddr(); }
/**Read the micro PC of this instruction. */
- const Addr microPC() const { return pc.microPC(); }
+ Addr microPC() const { return pc.microPC(); }
bool readPredicate()
{
template<class Impl>
Fault
-BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
+ Request::Flags flags)
{
instFlags[ReqMade] = true;
Request *req = NULL;
sreqHigh = savedSreqHigh;
} else {
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
- thread->contextId(), threadNumber);
+ thread->contextId());
req->taskId(cpu->taskId());
}
reqToVerify = new Request(*req);
}
- fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
+ fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
} else {
// Commit will have to clean up whatever happened. Set this
// instruction as executed.
this->setExecuted();
}
-
- if (fault != NoFault) {
- // Return a fixed value to keep simulation deterministic even
- // along misspeculated paths.
- if (data)
- bzero(data, size);
- }
}
if (traceData)
template<class Impl>
Fault
-BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
+ Request::Flags flags, uint64_t *res)
{
if (traceData)
traceData->setMem(addr, size, flags);
sreqHigh = savedSreqHigh;
} else {
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
- thread->contextId(), threadNumber);
+ thread->contextId());
req->taskId(cpu->taskId());