/*
- * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
+ * Copyright (c) 2011, 2013, 2016-2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- * Timothy M. Jones
*/
#ifndef __CPU_BASE_DYN_INST_HH__
#include "cpu/exetrace.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
-#include "cpu/o3/comm.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
+#include "debug/HtmCpu.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
SquashedInIQ, /// Instruction is squashed in the IQ
SquashedInLSQ, /// Instruction is squashed in the LSQ
SquashedInROB, /// Instruction is squashed in the ROB
+ PinnedRegsRenamed, /// Pinned registers are renamed
+ PinnedRegsWritten, /// Pinned registers are written back
+ PinnedRegsSquashDone, /// Regs pinning status updated after squash
RecoverInst, /// Is a recover instruction
BlockingInst, /// Is a blocking instruction
ThreadsyncWait, /// Is a thread synchronization instruction
EffAddrValid,
RecordResult,
Predicate,
+ MemAccPredicate,
PredTaken,
IsStrictlyOrdered,
ReqMade,
MemOpDone,
+ HtmFromTransaction,
MaxFlags
};
/** PC state for this instruction. */
TheISA::PCState pc;
+ private:
/* An amalgamation of a lot of boolean values into one */
std::bitset<MaxFlags> instFlags;
/** The status of this BaseDynInst. Several bits can be set. */
std::bitset<NumStatus> status;
+ protected:
/** Whether or not the source register is ready.
* @todo: Not sure this should be here vs the derived class.
*/
/** The memory request flags (from translation). */
unsigned memReqFlags;
- /** data address space ID, for loads & stores. */
- short asid;
-
/** The size of the request */
- uint8_t effSize;
+ unsigned effSize;
/** Pointer to the data for the memory access. */
uint8_t *memData;
// Need a copy of main request pointer to verify on writes.
RequestPtr reqToVerify;
+ private:
+ // hardware transactional memory
+ uint64_t htmUid;
+ uint64_t htmDepth;
+
protected:
/** Flattened register index of the destination registers of this
* instruction.
//
////////////////////////////////////////////
- void demapPage(Addr vaddr, uint64_t asn)
+ void
+ demapPage(Addr vaddr, uint64_t asn) override
{
cpu->demapPage(vaddr, asn);
}
- void demapInstPage(Addr vaddr, uint64_t asn)
+ void
+ demapInstPage(Addr vaddr, uint64_t asn)
{
cpu->demapPage(vaddr, asn);
}
- void demapDataPage(Addr vaddr, uint64_t asn)
+ void
+ demapDataPage(Addr vaddr, uint64_t asn)
{
cpu->demapPage(vaddr, asn);
}
- Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
+ Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
+ const std::vector<bool> &byte_enable=std::vector<bool>()) override;
+
+ Fault initiateHtmCmd(Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
- Request::Flags flags, uint64_t *res);
+ Request::Flags flags, uint64_t *res,
+ const std::vector<bool> &byte_enable=std::vector<bool>())
+ override;
+
+ Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
+ AtomicOpFunctorPtr amo_op) override;
/** True if the DTB address translation has started. */
bool translationStarted() const { return instFlags[TranslationStarted]; }
* snoop invalidate modifies the line, in which case we need to squash.
* If nothing modified the line the order doesn't matter.
*/
- bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
- void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
+ bool
+ possibleLoadViolation() const
+ {
+ return instFlags[PossibleLoadViolation];
+ }
+ void
+ possibleLoadViolation(bool f)
+ {
+ instFlags[PossibleLoadViolation] = f;
+ }
/** True if the address hit a external snoop while sitting in the LSQ.
* If this is true and a older instruction sees it, this instruction must
* Returns true if the DTB address translation is being delayed due to a hw
* page table walk.
*/
- bool isTranslationDelayed() const
+ bool
+ isTranslationDelayed() const
{
return (translationStarted() && !translationCompleted());
}
/** Returns the physical register index of the i'th destination
* register.
*/
- PhysRegIdPtr renamedDestRegIdx(int idx) const
+ PhysRegIdPtr
+ renamedDestRegIdx(int idx) const
{
return _destRegIdx[idx];
}
/** Returns the physical register index of the i'th source register. */
- PhysRegIdPtr renamedSrcRegIdx(int idx) const
+ PhysRegIdPtr
+ renamedSrcRegIdx(int idx) const
{
assert(TheISA::MaxInstSrcRegs > idx);
return _srcRegIdx[idx];
/** Returns the flattened register index of the i'th destination
* register.
*/
- const RegId& flattenedDestRegIdx(int idx) const
+ const RegId &
+ flattenedDestRegIdx(int idx) const
{
return _flatDestRegIdx[idx];
}
/** Returns the physical register index of the previous physical register
* that remapped to the same logical register index.
*/
- PhysRegIdPtr prevDestRegIdx(int idx) const
+ PhysRegIdPtr
+ prevDestRegIdx(int idx) const
{
return _prevDestRegIdx[idx];
}
/** Renames a destination register to a physical register. Also records
* the previous physical register that the logical register mapped to.
*/
- void renameDestReg(int idx,
- PhysRegIdPtr renamed_dest,
- PhysRegIdPtr previous_rename)
+ void
+ renameDestReg(int idx, PhysRegIdPtr renamed_dest,
+ PhysRegIdPtr previous_rename)
{
_destRegIdx[idx] = renamed_dest;
_prevDestRegIdx[idx] = previous_rename;
+ if (renamed_dest->isPinned())
+ setPinnedRegsRenamed();
}
/** Renames a source logical register to the physical register which
* has/will produce that logical register's result.
* @todo: add in whether or not the source register is ready.
*/
- void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
+ void
+ renameSrcReg(int idx, PhysRegIdPtr renamed_src)
{
_srcRegIdx[idx] = renamed_src;
}
/** Flattens a destination architectural register index into a logical
* index.
*/
- void flattenDestReg(int idx, const RegId& flattened_dest)
+ void
+ flattenDestReg(int idx, const RegId &flattened_dest)
{
_flatDestRegIdx[idx] = flattened_dest;
}
uint32_t socketId() const { return cpu->socketId(); }
/** Read this CPU's data requestor ID */
- MasterID masterId() const { return cpu->dataMasterId(); }
+ RequestorID requestorId() const { return cpu->dataRequestorId(); }
/** Read this context's system-wide ID **/
ContextID contextId() const { return thread->contextId(); }
bool doneTargCalc() { return false; }
/** Set the predicted target of this current instruction. */
- void setPredTarg(const TheISA::PCState &_predPC)
- {
- predPC = _predPC;
- }
+ void setPredTarg(const TheISA::PCState &_predPC) { predPC = _predPC; }
const TheISA::PCState &readPredTarg() { return predPC; }
Addr predMicroPC() { return predPC.microPC(); }
/** Returns whether the instruction was predicted taken or not. */
- bool readPredTaken()
- {
- return instFlags[PredTaken];
- }
+ bool readPredTaken() { return instFlags[PredTaken]; }
- void setPredTaken(bool predicted_taken)
+ void
+ setPredTaken(bool predicted_taken)
{
instFlags[PredTaken] = predicted_taken;
}
/** Returns whether the instruction mispredicted. */
- bool mispredicted()
+ bool
+ mispredicted()
{
TheISA::PCState tempPC = pc;
TheISA::advancePC(tempPC, staticInst);
bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
- bool isSerializeBefore() const
- { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
- bool isSerializeAfter() const
- { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
+ bool
+ isSerializeBefore() const
+ {
+ return staticInst->isSerializeBefore() || status[SerializeBefore];
+ }
+ bool
+ isSerializeAfter() const
+ {
+ return staticInst->isSerializeAfter() || status[SerializeAfter];
+ }
bool isSquashAfter() const { return staticInst->isSquashAfter(); }
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
bool isLastMicroop() const { return staticInst->isLastMicroop(); }
bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
bool isMicroBranch() const { return staticInst->isMicroBranch(); }
+ // hardware transactional memory
+ bool isHtmStart() const { return staticInst->isHtmStart(); }
+ bool isHtmStop() const { return staticInst->isHtmStop(); }
+ bool isHtmCancel() const { return staticInst->isHtmCancel(); }
+ bool isHtmCmd() const { return staticInst->isHtmCmd(); }
+
+ uint64_t
+ getHtmTransactionUid() const override
+ {
+ assert(instFlags[HtmFromTransaction]);
+ return this->htmUid;
+ }
+
+ uint64_t
+ newHtmTransactionUid() const override
+ {
+ panic("Not yet implemented\n");
+ return 0;
+ }
+
+ bool
+ inHtmTransactionalState() const override
+ {
+ return instFlags[HtmFromTransaction];
+ }
+
+ uint64_t
+ getHtmTransactionalDepth() const override
+ {
+ if (inHtmTransactionalState())
+ return this->htmDepth;
+ else
+ return 0;
+ }
+
+ void
+ setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth)
+ {
+ instFlags.set(HtmFromTransaction);
+ htmUid = htm_uid;
+ htmDepth = htm_depth;
+ }
+
+ void
+ clearHtmTransactionalState()
+ {
+ if (inHtmTransactionalState()) {
+ DPRINTF(HtmCpu,
+ "clearing instuction's transactional state htmUid=%u\n",
+ getHtmTransactionUid());
+
+ instFlags.reset(HtmFromTransaction);
+ htmUid = -1;
+ htmDepth = 0;
+ }
+ }
/** Temporarily sets this instruction as a serialize before instruction. */
void setSerializeBefore() { status.set(SerializeBefore); }
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
- int8_t numVecElemDestRegs() const
+ int8_t
+ numVecElemDestRegs() const
{
return staticInst->numVecElemDestRegs();
}
/** Pops a result off the instResult queue.
* If the result stack is empty, return the default value.
* */
- InstResult popResult(InstResult dflt = InstResult())
+ InstResult
+ popResult(InstResult dflt=InstResult())
{
if (!instResult.empty()) {
InstResult t = instResult.front();
/** @{ */
/** Scalar result. */
template<typename T>
- void setScalarResult(T&& t)
+ void
+ setScalarResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t),
/** Full vector result. */
template<typename T>
- void setVecResult(T&& t)
+ void
+ setVecResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t),
/** Vector element result. */
template<typename T>
- void setVecElemResult(T&& t)
+ void
+ setVecElemResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t),
/** Predicate result. */
template<typename T>
- void setVecPredResult(T&& t)
+ void
+ setVecPredResult(T &&t)
{
if (instFlags[RecordResult]) {
instResult.push(InstResult(std::forward<T>(t),
/** @} */
/** Records an integer register being set to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
+ void
+ setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
{
setScalarResult(val);
}
/** Records a CC register being set to a value. */
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void
+ setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
{
setScalarResult(val);
}
/** Record a vector register being set to a value */
- void setVecRegOperand(const StaticInst *si, int idx,
- const VecRegContainer& val)
+ void
+ setVecRegOperand(const StaticInst *si, int idx,
+ const VecRegContainer &val) override
{
setVecResult(val);
}
/** Records an fp register being set to an integer value. */
void
- setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
+ setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
{
setScalarResult(val);
}
/** Record a vector register being set to a value */
- void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
+ void
+ setVecElemOperand(const StaticInst *si, int idx,
+ const VecElem val) override
{
setVecElemResult(val);
}
/** Record a vector register being set to a value */
- void setVecPredRegOperand(const StaticInst *si, int idx,
- const VecPredRegContainer& val)
+ void
+ setVecPredRegOperand(const StaticInst *si, int idx,
+ const VecPredRegContainer &val) override
{
setVecPredResult(val);
}
void markSrcRegReady(RegIndex src_idx);
/** Returns if a source register is ready. */
- bool isReadySrcRegIdx(int idx) const
+ bool
+ isReadySrcRegIdx(int idx) const
{
return this->_readySrcRegIdx[idx];
}
bool isCommitted() const { return status[Committed]; }
/** Sets this instruction as squashed. */
- void setSquashed() { status.set(Squashed); }
+ void setSquashed();
/** Returns whether or not this instruction is squashed. */
bool isSquashed() const { return status[Squashed]; }
bool isInLSQ() const { return status[LsqEntry]; }
/** Sets this instruction as squashed in the LSQ. */
- void setSquashedInLSQ() { status.set(SquashedInLSQ);}
+ void setSquashedInLSQ() { status.set(SquashedInLSQ); status.set(Squashed);}
/** Returns whether or not this instruction is squashed in the LSQ. */
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
/** Returns whether or not this instruction is squashed in the ROB. */
bool isSquashedInROB() const { return status[SquashedInROB]; }
+ /** Returns whether pinned registers are renamed */
+ bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
+
+ /** Sets the destination registers as renamed */
+ void
+ setPinnedRegsRenamed()
+ {
+ assert(!status[PinnedRegsSquashDone]);
+ assert(!status[PinnedRegsWritten]);
+ status.set(PinnedRegsRenamed);
+ }
+
+ /** Returns whether destination registers are written */
+ bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
+
+ /** Sets destination registers as written */
+ void
+ setPinnedRegsWritten()
+ {
+ assert(!status[PinnedRegsSquashDone]);
+ assert(status[PinnedRegsRenamed]);
+ status.set(PinnedRegsWritten);
+ }
+
+ /** Return whether dest registers' pinning status updated after squash */
+ bool
+ isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
+
+ /** Sets dest registers' status updated after squash */
+ void
+ setPinnedRegsSquashDone() {
+ assert(!status[PinnedRegsSquashDone]);
+ status.set(PinnedRegsSquashDone);
+ }
+
/** Read the PC state of this instruction. */
- TheISA::PCState pcState() const { return pc; }
+ TheISA::PCState pcState() const override { return pc; }
/** Set the PC state of this instruction. */
- void pcState(const TheISA::PCState &val) { pc = val; }
+ void pcState(const TheISA::PCState &val) override { pc = val; }
/** Read the PC of this instruction. */
Addr instAddr() const { return pc.instAddr(); }
/**Read the micro PC of this instruction. */
Addr microPC() const { return pc.microPC(); }
- bool readPredicate() const
- {
- return instFlags[Predicate];
- }
+ bool readPredicate() const override { return instFlags[Predicate]; }
- void setPredicate(bool val)
+ void
+ setPredicate(bool val) override
{
instFlags[Predicate] = val;
}
}
- /** Sets the ASID. */
- void setASID(short addr_space_id) { asid = addr_space_id; }
- short getASID() { return asid; }
+ bool
+ readMemAccPredicate() const override
+ {
+ return instFlags[MemAccPredicate];
+ }
+
+ void
+ setMemAccPredicate(bool val) override
+ {
+ instFlags[MemAccPredicate] = val;
+ }
/** Sets the thread id. */
void setTid(ThreadID tid) { threadNumber = tid; }
void setThreadState(ImplState *state) { thread = state; }
/** Returns the thread context. */
- ThreadContext *tcBase() { return thread->getTC(); }
+ ThreadContext *tcBase() const override { return thread->getTC(); }
public:
/** Returns whether or not the eff. addr. source registers are ready. */
public:
/** Returns the number of consecutive store conditional failures. */
- unsigned int readStCondFailures() const
- { return thread->storeCondFailures; }
+ unsigned int
+ readStCondFailures() const override
+ {
+ return thread->storeCondFailures;
+ }
/** Sets the number of consecutive store conditional failures. */
- void setStCondFailures(unsigned int sc_failures)
- { thread->storeCondFailures = sc_failures; }
+ void
+ setStCondFailures(unsigned int sc_failures) override
+ {
+ thread->storeCondFailures = sc_failures;
+ }
public:
// monitor/mwait funtions
- void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
- bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
- void mwaitAtomic(ThreadContext *tc)
- { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
- AddressMonitor *getAddrMonitor()
- { return cpu->getCpuAddrMonitor(threadNumber); }
+ void
+ armMonitor(Addr address) override
+ {
+ cpu->armMonitor(threadNumber, address);
+ }
+ bool
+ mwait(PacketPtr pkt) override
+ {
+ return cpu->mwait(threadNumber, pkt);
+ }
+ void
+ mwaitAtomic(ThreadContext *tc) override
+ {
+ return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb);
+ }
+ AddressMonitor *
+ getAddrMonitor() override
+ {
+ return cpu->getCpuAddrMonitor(threadNumber);
+ }
};
template<class Impl>
Fault
BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
- Request::Flags flags)
+ Request::Flags flags,
+ const std::vector<bool> &byte_enable)
{
+ assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->pushRequest(
dynamic_cast<typename DynInstPtr::PtrType>(this),
- /* ld */ true, nullptr, size, addr, flags, nullptr);
+ /* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
+ byte_enable);
+}
+
+template<class Impl>
+Fault
+BaseDynInst<Impl>::initiateHtmCmd(Request::Flags flags)
+{
+ return cpu->pushRequest(
+ dynamic_cast<typename DynInstPtr::PtrType>(this),
+ /* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr);
}
template<class Impl>
Fault
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
- Request::Flags flags, uint64_t *res)
+ Request::Flags flags, uint64_t *res,
+ const std::vector<bool> &byte_enable)
+{
+ assert(byte_enable.empty() || byte_enable.size() == size);
+ return cpu->pushRequest(
+ dynamic_cast<typename DynInstPtr::PtrType>(this),
+ /* st */ false, data, size, addr, flags, res, nullptr,
+ byte_enable);
+}
+
+template<class Impl>
+Fault
+BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
+ Request::Flags flags,
+ AtomicOpFunctorPtr amo_op)
{
+ // atomic memory instructions do not have data to be written to memory yet
+ // since the atomic operations will be executed directly in cache/memory.
+ // Therefore, its `data` field is nullptr.
+ // Atomic memory requests need to carry their `amo_op` fields to cache/
+ // memory
return cpu->pushRequest(
dynamic_cast<typename DynInstPtr::PtrType>(this),
- /* st */ false, data, size, addr, flags, res);
+ /* atomic */ false, nullptr, size, addr, flags, nullptr,
+ std::move(amo_op));
}
#endif // __CPU_BASE_DYN_INST_HH__
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