#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
+#include "sim/tlb.hh"
/**
* @file
typedef typename std::list<DynInstPtr>::iterator ListIt;
enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
};
/** The StaticInst used by this BaseDynInst. */
/** InstRecord that tracks this instructions. */
Trace::InstRecord *traceData;
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+ void demapInstPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+ void demapDataPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+
/**
* Does a read to a given address.
* @param addr The address to read.
public:
- /** Count of total number of dynamic instructions. */
- static int instcount;
-
#ifdef DEBUG
void dumpSNList();
#endif
void dump(std::string &outstring);
/** Read this CPU's ID. */
- int readCpuId() { return cpu->readCpuId(); }
+ int cpuId() { return cpu->cpuId(); }
+
+ /** Read this context's system-wide ID **/
+ int contextId() { return thread->contextId(); }
/** Returns the fault type. */
Fault getFault() { return fault; }
//
// Instruction types. Forward checks to StaticInst object.
//
- bool isNop() const { return staticInst->isNop(); }
- bool isMemRef() const { return staticInst->isMemRef(); }
- bool isLoad() const { return staticInst->isLoad(); }
- bool isStore() const { return staticInst->isStore(); }
+ bool isNop() const { return staticInst->isNop(); }
+ bool isMemRef() const { return staticInst->isMemRef(); }
+ bool isLoad() const { return staticInst->isLoad(); }
+ bool isStore() const { return staticInst->isStore(); }
bool isStoreConditional() const
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
bool isCopy() const { return staticInst->isCopy(); }
- bool isInteger() const { return staticInst->isInteger(); }
- bool isFloating() const { return staticInst->isFloating(); }
- bool isControl() const { return staticInst->isControl(); }
- bool isCall() const { return staticInst->isCall(); }
- bool isReturn() const { return staticInst->isReturn(); }
- bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
+ bool isInteger() const { return staticInst->isInteger(); }
+ bool isFloating() const { return staticInst->isFloating(); }
+ bool isControl() const { return staticInst->isControl(); }
+ bool isCall() const { return staticInst->isCall(); }
+ bool isReturn() const { return staticInst->isReturn(); }
+ bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
- bool isCondCtrl() const { return staticInst->isCondCtrl(); }
- bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
+ bool isCondCtrl() const { return staticInst->isCondCtrl(); }
+ bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
- bool isMacroOp() const { return staticInst->isMacroOp(); }
- bool isMicroOp() const { return staticInst->isMicroOp(); }
+ bool isSyscall() const { return staticInst->isSyscall(); }
+ bool isMacroop() const { return staticInst->isMacroop(); }
+ bool isMicroop() const { return staticInst->isMicroop(); }
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
- bool isLastMicroOp() const { return staticInst->isLastMicroOp(); }
- bool isFirstMicroOp() const { return staticInst->isFirstMicroOp(); }
+ bool isLastMicroop() const { return staticInst->isLastMicroop(); }
+ bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
bool isMicroBranch() const { return staticInst->isMicroBranch(); }
/** Temporarily sets this instruction as a serialize before instruction. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
/** Returns the number of source registers. */
- int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
+ int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
/** Returns the number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
-
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- delete req;
- return TheISA::genAlignmentFault();
- }
+ req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataReadReq(req, thread);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
if (req->isUncacheable())
isUncacheable = true;
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
-
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- delete req;
- return TheISA::genAlignmentFault();
- }
+ req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataWriteReq(req, thread);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
if (req->isUncacheable())
isUncacheable = true;