cpus: fix cpu progress event

[gem5.git] / src / cpu / base_dyn_inst.hh

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 3520fafaa2c14e882647e1dacc95716d61b9de70..ed0054402c4eb298ebb5be1522aa88eafab76d25 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -46,6 +46,7 @@
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "sim/system.hh"
+#include "sim/tlb.hh"
 
 /**
  * @file
@@ -115,9 +116,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     /**
      * Does a write to a given address.
      * @param data The data to be written.
@@ -130,9 +128,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     Fault write(T data, Addr addr, unsigned flags,
                         uint64_t *res);
 
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     void prefetch(Addr addr, unsigned flags);
     void writeHint(Addr addr, int size, unsigned flags);
     Fault copySrcTranslate(Addr src);
@@ -258,9 +253,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
   public:
 
-    /** Count of total number of dynamic instructions. */
-    static int instcount;
-
 #ifdef DEBUG
     void dumpSNList();
 #endif
@@ -859,29 +851,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     { thread->storeCondFailures = sc_failures; }
 };
 
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
-
-    fault = cpu->translateDataReadReq(req, thread);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 template<class Impl>
 template<class T>
 inline Fault
@@ -892,7 +861,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->translateDataReadReq(req, thread);
+    fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
 
     if (req->isUncacheable())
         isUncacheable = true;
@@ -933,29 +902,6 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     return fault;
 }
 
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
-
-    fault = cpu->translateDataWriteReq(req, thread);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 template<class Impl>
 template<class T>
 inline Fault
@@ -971,7 +917,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->translateDataWriteReq(req, thread);
+    fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
 
     if (req->isUncacheable())
         isUncacheable = true;