#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
+#include "sim/tlb.hh"
/**
* @file
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
- Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags);
-
/**
* Does a write to a given address.
* @param data The data to be written.
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
- Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags);
-
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
Fault copySrcTranslate(Addr src);
{ thread->storeCondFailures = sc_failures; }
};
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags)
-{
- if (traceData) {
- traceData->setAddr(vaddr);
- }
-
- reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->contextId(), threadNumber);
-
- fault = cpu->translateDataReadReq(req, thread);
-
- if (fault == NoFault)
- paddr = req->getPaddr();
-
- delete req;
- return fault;
-}
-
template<class Impl>
template<class T>
inline Fault
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataReadReq(req, thread);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
if (req->isUncacheable())
isUncacheable = true;
return fault;
}
-template<class Impl>
-Fault
-BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
- int size, unsigned flags)
-{
- if (traceData) {
- traceData->setAddr(vaddr);
- }
-
- reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->contextId(), threadNumber);
-
- fault = cpu->translateDataWriteReq(req, thread);
-
- if (fault == NoFault)
- paddr = req->getPaddr();
-
- delete req;
- return fault;
-}
-
template<class Impl>
template<class T>
inline Fault
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->translateDataWriteReq(req, thread);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
if (req->isUncacheable())
isUncacheable = true;