typedef typename std::list<DynInstPtr>::iterator ListIt;
enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
};
/** The StaticInst used by this BaseDynInst. */
/** InstRecord that tracks this instructions. */
Trace::InstRecord *traceData;
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+ void demapInstPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+ void demapDataPage(Addr vaddr, uint64_t asn)
+ {
+ cpu->demapPage(vaddr, asn);
+ }
+
/**
* Does a read to a given address.
* @param addr The address to read.
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
+ Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags);
+
/**
* Does a write to a given address.
* @param data The data to be written.
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
+ Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags);
+
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
Fault copySrcTranslate(Addr src);
/** The kind of fault this instruction has generated. */
Fault fault;
- /** The memory request. */
- Request *req;
-
/** Pointer to the data for the memory access. */
uint8_t *memData;
/** The effective virtual address (lds & stores only). */
Addr effAddr;
+ /** Is the effective virtual address valid. */
+ bool effAddrValid;
+
/** The effective physical address. */
Addr physEffAddr;
/** PC of this instruction. */
Addr PC;
+ /** Micro PC of this instruction. */
+ Addr microPC;
+
protected:
/** Next non-speculative PC. It is not filled in at fetch, but rather
* once the target of the branch is truly known (either decode or
/** Next non-speculative NPC. Target PC for Mips or Sparc. */
Addr nextNPC;
+ /** Next non-speculative micro PC. */
+ Addr nextMicroPC;
+
/** Predicted next PC. */
Addr predPC;
/** Predicted next NPC. */
Addr predNPC;
+ /** Predicted next microPC */
+ Addr predMicroPC;
+
/** If this is a branch that was predicted taken */
bool predTaken;
public:
- /** Count of total number of dynamic instructions. */
- static int instcount;
-
#ifdef DEBUG
void dumpSNList();
#endif
{
_flatDestRegIdx[idx] = flattened_dest;
}
+ /** BaseDynInst constructor given a binary instruction.
+ * @param staticInst A StaticInstPtr to the underlying instruction.
+ * @param PC The PC of the instruction.
+ * @param pred_PC The predicted next PC.
+ * @param pred_NPC The predicted next NPC.
+ * @param seq_num The sequence number of the instruction.
+ * @param cpu Pointer to the instruction's CPU.
+ */
+ BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
+ Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
+ InstSeqNum seq_num, ImplCPU *cpu);
/** BaseDynInst constructor given a binary instruction.
* @param inst The binary instruction.
* @param seq_num The sequence number of the instruction.
* @param cpu Pointer to the instruction's CPU.
*/
- BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC,
- Addr pred_PC, Addr pred_NPC,
+ BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
+ Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
InstSeqNum seq_num, ImplCPU *cpu);
/** BaseDynInst constructor given a StaticInst pointer.
void dump(std::string &outstring);
/** Read this CPU's ID. */
- int readCpuId() { return cpu->readCpuId(); }
+ int cpuId() { return cpu->cpuId(); }
+
+ /** Read this context's system-wide ID **/
+ int contextId() { return thread->contextId(); }
/** Returns the fault type. */
Fault getFault() { return fault; }
#endif
}
+ Addr readNextMicroPC()
+ {
+ return nextMicroPC;
+ }
+
/** Set the predicted target of this current instruction. */
- void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
+ void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
+ Addr predicted_MicroPC)
{
predPC = predicted_PC;
predNPC = predicted_NPC;
+ predMicroPC = predicted_MicroPC;
}
/** Returns the predicted PC immediately after the branch. */
/** Returns the predicted PC two instructions after the branch */
Addr readPredNPC() { return predNPC; }
+ /** Returns the predicted micro PC after the branch */
+ Addr readPredMicroPC() { return predMicroPC; }
+
/** Returns whether the instruction was predicted taken or not. */
bool readPredTaken()
{
bool mispredicted()
{
return readPredPC() != readNextPC() ||
- readPredNPC() != readNextNPC();
+ readPredNPC() != readNextNPC() ||
+ readPredMicroPC() != readNextMicroPC();
}
//
// Instruction types. Forward checks to StaticInst object.
//
- bool isNop() const { return staticInst->isNop(); }
- bool isMemRef() const { return staticInst->isMemRef(); }
- bool isLoad() const { return staticInst->isLoad(); }
- bool isStore() const { return staticInst->isStore(); }
+ bool isNop() const { return staticInst->isNop(); }
+ bool isMemRef() const { return staticInst->isMemRef(); }
+ bool isLoad() const { return staticInst->isLoad(); }
+ bool isStore() const { return staticInst->isStore(); }
bool isStoreConditional() const
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
bool isCopy() const { return staticInst->isCopy(); }
- bool isInteger() const { return staticInst->isInteger(); }
- bool isFloating() const { return staticInst->isFloating(); }
- bool isControl() const { return staticInst->isControl(); }
- bool isCall() const { return staticInst->isCall(); }
- bool isReturn() const { return staticInst->isReturn(); }
- bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
+ bool isInteger() const { return staticInst->isInteger(); }
+ bool isFloating() const { return staticInst->isFloating(); }
+ bool isControl() const { return staticInst->isControl(); }
+ bool isCall() const { return staticInst->isCall(); }
+ bool isReturn() const { return staticInst->isReturn(); }
+ bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
- bool isCondCtrl() const { return staticInst->isCondCtrl(); }
- bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
+ bool isCondCtrl() const { return staticInst->isCondCtrl(); }
+ bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
+ bool isSyscall() const { return staticInst->isSyscall(); }
+ bool isMacroop() const { return staticInst->isMacroop(); }
+ bool isMicroop() const { return staticInst->isMicroop(); }
+ bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
+ bool isLastMicroop() const { return staticInst->isLastMicroop(); }
+ bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
+ bool isMicroBranch() const { return staticInst->isMicroBranch(); }
/** Temporarily sets this instruction as a serialize before instruction. */
void setSerializeBefore() { status.set(SerializeBefore); }
Addr branchTarget() const { return staticInst->branchTarget(PC); }
/** Returns the number of source registers. */
- int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
+ int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
/** Returns the number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
/** Returns whether or not this instruction is ready to issue. */
bool readyToIssue() const { return status[CanIssue]; }
+ /** Clears this instruction being able to issue. */
+ void clearCanIssue() { status.reset(CanIssue); }
+
/** Sets this instruction as issued from the IQ. */
void setIssued() { status.set(Issued); }
/** Returns whether or not this instruction has issued. */
bool isIssued() const { return status[Issued]; }
+ /** Clears this instruction as being issued. */
+ void clearIssued() { status.reset(Issued); }
+
/** Sets this instruction as executed. */
void setExecuted() { status.set(Executed); }
/** Read the PC of this instruction. */
const Addr readPC() const { return PC; }
+ /**Read the micro PC of this instruction. */
+ const Addr readMicroPC() const { return microPC; }
+
/** Set the next PC of this instruction (its actual target). */
- void setNextPC(uint64_t val)
+ void setNextPC(Addr val)
{
nextPC = val;
}
/** Set the next NPC of this instruction (the target in Mips or Sparc).*/
- void setNextNPC(uint64_t val)
+ void setNextNPC(Addr val)
{
+#if ISA_HAS_DELAY_SLOT
nextNPC = val;
+#endif
+ }
+
+ void setNextMicroPC(Addr val)
+ {
+ nextMicroPC = val;
}
/** Sets the ASID. */
*/
bool eaCalcDone;
+ /** Is this instruction's memory access uncacheable. */
+ bool isUncacheable;
+
+ /** Has this instruction generated a memory request. */
+ bool reqMade;
+
public:
/** Sets the effective address. */
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
/** Whether or not the memory operation is done. */
bool memOpDone;
+ /** Is this instruction's memory access uncacheable. */
+ bool uncacheable() { return isUncacheable; }
+
+ /** Has this instruction generated a memory request. */
+ bool hasRequest() { return reqMade; }
+
public:
/** Load queue index. */
int16_t lqIdx;
{ thread->storeCondFailures = sc_failures; }
};
+template<class Impl>
+Fault
+BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(vaddr);
+ }
+
+ reqMade = true;
+ Request *req = new Request();
+ req->setVirt(asid, vaddr, size, flags, PC);
+ req->setThreadContext(thread->contextId(), threadNumber);
+
+ fault = cpu->translateDataReadReq(req, thread);
+
+ if (fault == NoFault)
+ paddr = req->getPaddr();
+
+ delete req;
+ return fault;
+}
+
template<class Impl>
template<class T>
inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
- // Sometimes reads will get retried, so they may come through here
- // twice.
- if (!req) {
- req = new Request();
- req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
- } else {
- assert(addr == req->getVaddr());
- }
-
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- return TheISA::genAlignmentFault();
- }
+ reqMade = true;
+ Request *req = new Request();
+ req->setVirt(asid, addr, sizeof(T), flags, this->PC);
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataReadReq(req, thread);
+ if (req->isUncacheable())
+ isUncacheable = true;
+
if (fault == NoFault) {
effAddr = req->getVaddr();
+ effAddrValid = true;
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
// Commit will have to clean up whatever happened. Set this
// instruction as executed.
this->setExecuted();
+ delete req;
}
if (traceData) {
return fault;
}
+template<class Impl>
+Fault
+BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
+ int size, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(vaddr);
+ }
+
+ reqMade = true;
+ Request *req = new Request();
+ req->setVirt(asid, vaddr, size, flags, PC);
+ req->setThreadContext(thread->contextId(), threadNumber);
+
+ fault = cpu->translateDataWriteReq(req, thread);
+
+ if (fault == NoFault)
+ paddr = req->getPaddr();
+
+ delete req;
+ return fault;
+}
+
template<class Impl>
template<class T>
inline Fault
traceData->setData(data);
}
- assert(req == NULL);
-
- req = new Request();
+ reqMade = true;
+ Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
-
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- return TheISA::genAlignmentFault();
- }
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataWriteReq(req, thread);
+ if (req->isUncacheable())
+ isUncacheable = true;
+
if (fault == NoFault) {
effAddr = req->getVaddr();
+ effAddrValid = true;
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
+
+ if (req->isCondSwap()) {
+ assert(res);
+ req->setExtraData(*res);
+ }
#if 0
if (cpu->system->memctrl->badaddr(physEffAddr)) {
fault = TheISA::genMachineCheckFault();
#else
fault = cpu->write(req, data, sqIdx);
#endif
- }
-
- if (res) {
- // always return some result to keep misspeculated paths
- // (which will ignore faults) deterministic
- *res = (fault == NoFault) ? req->getExtraData() : 0;
+ } else {
+ delete req;
}
return fault;
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