/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
#include <iostream>
#include <set>
-#include <string>
#include <sstream>
+#include <string>
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
+#include "debug/DynInst.hh"
+#include "debug/IQ.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
-#define NOHASH
-#ifndef NOHASH
-
-#include "base/hashmap.hh"
-
-unsigned int MyHashFunc(const BaseDynInst *addr)
-{
- unsigned a = (unsigned)addr;
- unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
-
- return hash;
-}
-
-typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
-my_hash_t;
-
-my_hash_t thishash;
-#endif
-
template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
- Addr inst_PC, Addr inst_NPC,
- Addr inst_MicroPC,
- Addr pred_PC, Addr pred_NPC,
- Addr pred_MicroPC,
+ StaticInstPtr _macroop,
+ TheISA::PCState _pc, TheISA::PCState _predPC,
InstSeqNum seq_num, ImplCPU *cpu)
- : staticInst(_staticInst), traceData(NULL), cpu(cpu)
+ : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
{
seqNum = seq_num;
- bool nextIsMicro =
- staticInst->isMicroop() && !staticInst->isLastMicroop();
-
- PC = inst_PC;
- microPC = inst_MicroPC;
- if (nextIsMicro) {
- nextPC = inst_PC;
- nextNPC = inst_NPC;
- nextMicroPC = microPC + 1;
- } else {
- nextPC = inst_NPC;
- nextNPC = nextPC + sizeof(TheISA::MachInst);
- nextMicroPC = 0;
- }
- predPC = pred_PC;
- predNPC = pred_NPC;
- predMicroPC = pred_MicroPC;
- predTaken = false;
+ pc = _pc;
+ predPC = _predPC;
initVars();
}
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
- Addr inst_PC, Addr inst_NPC,
- Addr inst_MicroPC,
- Addr pred_PC, Addr pred_NPC,
- Addr pred_MicroPC,
- InstSeqNum seq_num, ImplCPU *cpu)
- : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
-{
- seqNum = seq_num;
-
- bool nextIsMicro =
- staticInst->isMicroop() && !staticInst->isLastMicroop();
-
- PC = inst_PC;
- microPC = inst_MicroPC;
- if (nextIsMicro) {
- nextPC = inst_PC;
- nextNPC = inst_NPC;
- nextMicroPC = microPC + 1;
- } else {
- nextPC = inst_NPC;
- nextNPC = nextPC + sizeof(TheISA::MachInst);
- nextMicroPC = 0;
- }
- predPC = pred_PC;
- predNPC = pred_NPC;
- predMicroPC = pred_MicroPC;
- predTaken = false;
-
- initVars();
-}
-
-template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
- : staticInst(_staticInst), traceData(NULL)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
+ StaticInstPtr _macroop)
+ : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
{
seqNum = 0;
initVars();
{
memData = NULL;
effAddr = 0;
- effAddrValid = false;
physEffAddr = 0;
-
- isUncacheable = false;
- reqMade = false;
readyRegs = 0;
- instResult.integer = 0;
- recordResult = true;
-
status.reset();
- eaCalcDone = false;
- memOpDone = false;
+ instFlags.reset();
+ instFlags[RecordResult] = true;
+ instFlags[Predicate] = true;
lqIdx = -1;
sqIdx = -1;
#ifdef DEBUG
cpu->snList.insert(seqNum);
#endif
+
+ reqToVerify = NULL;
}
template <class Impl>
#ifdef DEBUG
cpu->snList.erase(seqNum);
#endif
+
+ if (reqToVerify)
+ delete reqToVerify;
}
#ifdef DEBUG
}
#endif
-template <class Impl>
-void
-BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
-{
- // This is the "functional" implementation of prefetch. Not much
- // happens here since prefetches don't affect the architectural
- // state.
-/*
- // Generate a MemReq so we can translate the effective address.
- MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
- req->asid = asid;
-
- // Prefetches never cause faults.
- fault = NoFault;
-
- // note this is a local, not BaseDynInst::fault
- Fault trans_fault = cpu->translateDataReadReq(req);
-
- if (trans_fault == NoFault && !(req->isUncacheable())) {
- // It's a valid address to cacheable space. Record key MemReq
- // parameters so we can generate another one just like it for
- // the timing access without calling translate() again (which
- // might mess up the TLB).
- effAddr = req->vaddr;
- physEffAddr = req->paddr;
- memReqFlags = req->flags;
- } else {
- // Bogus address (invalid or uncacheable space). Mark it by
- // setting the eff_addr to InvalidAddr.
- effAddr = physEffAddr = MemReq::inval_addr;
- }
-
- if (traceData) {
- traceData->setAddr(addr);
- }
-*/
-}
-
-template <class Impl>
-void
-BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
-{
- // Not currently supported.
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copySrcTranslate(Addr src)
-{
- // Not currently supported.
- return NoFault;
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-template <class Impl>
-Fault
-BaseDynInst<Impl>::copy(Addr dest)
-{
- // Not currently supported.
- return NoFault;
-}
-
template <class Impl>
void
BaseDynInst<Impl>::dump()
{
- cprintf("T%d : %#08d `", threadNumber, PC);
- std::cout << staticInst->disassemble(PC);
+ cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
+ std::cout << staticInst->disassemble(pc.instAddr());
cprintf("'\n");
}
BaseDynInst<Impl>::dump(std::string &outstring)
{
std::ostringstream s;
- s << "T" << threadNumber << " : 0x" << PC << " "
- << staticInst->disassemble(PC);
+ s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
+ << staticInst->disassemble(pc.instAddr());
outstring = s.str();
}
void
BaseDynInst<Impl>::markSrcRegReady()
{
+ DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
+ seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
if (++readyRegs == numSrcRegs()) {
setCanIssue();
}
projects / gem5.git / blobdiff