#include "base/cprintf.hh"
#include "base/trace.hh"
-
-#include "arch/faults.hh"
+#include "config/the_isa.hh"
+#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "mem/request.hh"
-
-#include "cpu/base_dyn_inst.hh"
-
-using namespace std;
-using namespace TheISA;
+#include "sim/faults.hh"
#define NOHASH
#ifndef NOHASH
#endif
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
- Addr pred_PC, InstSeqNum seq_num,
- ImplCPU *cpu)
- : staticInst(machInst), traceData(NULL), cpu(cpu)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
+ Addr inst_PC, Addr inst_NPC,
+ Addr inst_MicroPC,
+ Addr pred_PC, Addr pred_NPC,
+ Addr pred_MicroPC,
+ InstSeqNum seq_num, ImplCPU *cpu)
+ : staticInst(_staticInst), traceData(NULL), cpu(cpu)
{
seqNum = seq_num;
+ bool nextIsMicro =
+ staticInst->isMicroop() && !staticInst->isLastMicroop();
+
PC = inst_PC;
- nextPC = PC + sizeof(MachInst);
- nextNPC = nextPC + sizeof(MachInst);
+ microPC = inst_MicroPC;
+ if (nextIsMicro) {
+ nextPC = inst_PC;
+ nextNPC = inst_NPC;
+ nextMicroPC = microPC + 1;
+ } else {
+ nextPC = inst_NPC;
+ nextNPC = nextPC + sizeof(TheISA::MachInst);
+ nextMicroPC = 0;
+ }
predPC = pred_PC;
+ predNPC = pred_NPC;
+ predMicroPC = pred_MicroPC;
+ predTaken = false;
+
+ initVars();
+}
+
+template <class Impl>
+BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
+ Addr inst_PC, Addr inst_NPC,
+ Addr inst_MicroPC,
+ Addr pred_PC, Addr pred_NPC,
+ Addr pred_MicroPC,
+ InstSeqNum seq_num, ImplCPU *cpu)
+ : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
+{
+ seqNum = seq_num;
+
+ bool nextIsMicro =
+ staticInst->isMicroop() && !staticInst->isLastMicroop();
+
+ PC = inst_PC;
+ microPC = inst_MicroPC;
+ if (nextIsMicro) {
+ nextPC = inst_PC;
+ nextNPC = inst_NPC;
+ nextMicroPC = microPC + 1;
+ } else {
+ nextPC = inst_NPC;
+ nextNPC = nextPC + sizeof(TheISA::MachInst);
+ nextMicroPC = 0;
+ }
+ predPC = pred_PC;
+ predNPC = pred_NPC;
+ predMicroPC = pred_MicroPC;
+ predTaken = false;
initVars();
}
void
BaseDynInst<Impl>::initVars()
{
- req = NULL;
memData = NULL;
effAddr = 0;
+ effAddrValid = false;
physEffAddr = 0;
+ isUncacheable = false;
+ reqMade = false;
readyRegs = 0;
instResult.integer = 0;
+ recordResult = true;
status.reset();
// Initialize the fault to be NoFault.
fault = NoFault;
- ++instcount;
+#ifndef NDEBUG
+ ++cpu->instcount;
- if (instcount > 1500) {
- cpu->dumpInsts();
+ if (cpu->instcount > 1500) {
#ifdef DEBUG
+ cpu->dumpInsts();
dumpSNList();
#endif
- assert(instcount <= 1500);
+ assert(cpu->instcount <= 1500);
}
- DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
- seqNum, instcount);
+ DPRINTF(DynInst,
+ "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
+ seqNum, cpu->name(), cpu->instcount);
+#endif
#ifdef DEBUG
cpu->snList.insert(seqNum);
template <class Impl>
BaseDynInst<Impl>::~BaseDynInst()
{
- if (req) {
- delete req;
- }
-
if (memData) {
delete [] memData;
}
fault = NoFault;
- --instcount;
+#ifndef NDEBUG
+ --cpu->instcount;
- DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
- seqNum, instcount);
+ DPRINTF(DynInst,
+ "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
+ seqNum, cpu->name(), cpu->instcount);
+#endif
#ifdef DEBUG
cpu->snList.erase(seqNum);
#endif
// note this is a local, not BaseDynInst::fault
Fault trans_fault = cpu->translateDataReadReq(req);
- if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
+ if (trans_fault == NoFault && !(req->isUncacheable())) {
// It's a valid address to cacheable space. Record key MemReq
// parameters so we can generate another one just like it for
// the timing access without calling translate() again (which
BaseDynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, PC);
- cout << staticInst->disassemble(PC);
+ std::cout << staticInst->disassemble(PC);
cprintf("'\n");
}
BaseDynInst<Impl>::markSrcRegReady()
{
if (++readyRegs == numSrcRegs()) {
- status.set(CanIssue);
+ setCanIssue();
}
}