Add x86 version of call to "decode"

[gem5.git] / src / cpu / base_dyn_inst_impl.hh

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index f2109e88d7e31e5b8932ec1427ea568d8ef998f0..c3d71e42842c5936d38d2a45b8c54f8405b8223a 100644 (file)
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -62,17 +62,20 @@ my_hash_t thishash;
 #endif
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
-                               Addr pred_PC, InstSeqNum seq_num,
-                               ImplCPU *cpu)
+BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst,
+                               Addr inst_PC, Addr inst_NPC,
+                               Addr pred_PC, Addr pred_NPC,
+                               InstSeqNum seq_num, ImplCPU *cpu)
   : staticInst(machInst), traceData(NULL), cpu(cpu)
 {
     seqNum = seq_num;
 
     PC = inst_PC;
-    nextPC = PC + sizeof(TheISA::MachInst);
+    nextPC = inst_NPC;
     nextNPC = nextPC + sizeof(TheISA::MachInst);
     predPC = pred_PC;
+    predNPC = pred_NPC;
+    predTaken = false;
 
     initVars();
 }
@@ -97,6 +100,7 @@ BaseDynInst<Impl>::initVars()
     readyRegs = 0;
 
     instResult.integer = 0;
+    recordResult = true;
 
     status.reset();
 
@@ -193,7 +197,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     // note this is a local, not BaseDynInst::fault
     Fault trans_fault = cpu->translateDataReadReq(req);
 
-    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
+    if (trans_fault == NoFault && !(req->isUncacheable())) {
         // It's a valid address to cacheable space.  Record key MemReq
         // parameters so we can generate another one just like it for
         // the timing access without calling translate() again (which