/*
+ * Copyright (c) 2011,2013,2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
*/
+#include "cpu/checker/cpu.hh"
+
#include <list>
#include <string>
+#include "arch/generic/tlb.hh"
+#include "arch/vtophys.hh"
#include "cpu/base.hh"
-#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
-#include "mem/packet_impl.hh"
-#include "sim/byteswap.hh"
-
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#include "kern/kernel_stats.hh"
-#endif // FULL_SYSTEM
+#include "cpu/thread_context.hh"
+#include "cpu/utils.hh"
+#include "params/CheckerCPU.hh"
+#include "sim/full_system.hh"
using namespace std;
-//The CheckerCPU does alpha only
-using namespace AlphaISA;
+using namespace TheISA;
void
CheckerCPU::init()
{
+ masterId = systemPtr->getMasterId(this);
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), thread(NULL), tc(NULL)
+ : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
+ tc(NULL), thread(NULL),
+ unverifiedReq(nullptr),
+ unverifiedMemData(nullptr)
{
- memReq = NULL;
+ curStaticInst = NULL;
+ curMacroStaticInst = NULL;
numInst = 0;
startNumInst = 0;
startNumLoad = 0;
youngestSN = 0;
- changedPC = willChangePC = changedNextPC = false;
+ changedPC = willChangePC = false;
exitOnError = p->exitOnError;
warnOnlyOnLoadError = p->warnOnlyOnLoadError;
-#if FULL_SYSTEM
itb = p->itb;
dtb = p->dtb;
- systemPtr = NULL;
-#else
- process = p->process;
-#endif
+ workload = p->workload;
- result.integer = 0;
+ updateOnError = true;
}
CheckerCPU::~CheckerCPU()
{
}
-void
-CheckerCPU::setMemory(MemObject *mem)
-{
-#if !FULL_SYSTEM
- memPtr = mem;
- thread = new SimpleThread(this, /* thread_num */ 0, process,
- /* asid */ 0, mem);
-
- thread->setStatus(ThreadContext::Suspended);
- tc = thread->getTC();
- threadContexts.push_back(tc);
-#endif
-}
-
void
CheckerCPU::setSystem(System *system)
{
-#if FULL_SYSTEM
+ const Params *p(dynamic_cast<const Params *>(_params));
+
systemPtr = system;
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+ if (FullSystem) {
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
+ p->isa[0], false);
+ } else {
+ thread = new SimpleThread(this, 0, systemPtr,
+ workload.size() ? workload[0] : NULL,
+ itb, dtb, p->isa[0]);
+ }
- thread->setStatus(ThreadContext::Suspended);
tc = thread->getTC();
threadContexts.push_back(tc);
- delete thread->kernelStats;
thread->kernelStats = NULL;
-#endif
+ // Thread should never be null after this
+ assert(thread != NULL);
}
void
-CheckerCPU::setIcachePort(Port *icache_port)
+CheckerCPU::setIcachePort(MasterPort *icache_port)
{
icachePort = icache_port;
}
void
-CheckerCPU::setDcachePort(Port *dcache_port)
+CheckerCPU::setDcachePort(MasterPort *dcache_port)
{
dcachePort = dcache_port;
}
void
-CheckerCPU::serialize(ostream &os)
+CheckerCPU::serialize(ostream &os) const
{
-/*
- BaseCPU::serialize(os);
- SERIALIZE_SCALAR(inst);
- nameOut(os, csprintf("%s.xc", name()));
- thread->serialize(os);
- cacheCompletionEvent.serialize(os);
-*/
}
void
-CheckerCPU::unserialize(Checkpoint *cp, const string §ion)
+CheckerCPU::unserialize(CheckpointIn &cp)
{
-/*
- BaseCPU::unserialize(cp, section);
- UNSERIALIZE_SCALAR(inst);
- thread->unserialize(cp, csprintf("%s.xc", section));
-*/
}
-Fault
-CheckerCPU::copySrcTranslate(Addr src)
+RequestPtr
+CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size,
+ Request::Flags flags,
+ const std::vector<bool>& byte_enable,
+ int& frag_size, int& size_left) const
{
- panic("Unimplemented!");
-}
+ frag_size = std::min(
+ cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()),
+ (Addr) size_left);
+ size_left -= frag_size;
+
+ RequestPtr mem_req;
+
+ if (!byte_enable.empty()) {
+ // Set up byte-enable mask for the current fragment
+ auto it_start = byte_enable.cbegin() + (size - (frag_size +
+ size_left));
+ auto it_end = byte_enable.cbegin() + (size - size_left);
+ if (isAnyActiveElement(it_start, it_end)) {
+ mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
+ flags, masterId, thread->pcState().instAddr(),
+ tc->contextId());
+ mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
+ }
+ } else {
+ mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
+ flags, masterId, thread->pcState().instAddr(),
+ tc->contextId());
+ }
-Fault
-CheckerCPU::copy(Addr dest)
-{
- panic("Unimplemented!");
+ return mem_req;
}
-template <class T>
Fault
-CheckerCPU::read(Addr addr, T &data, unsigned flags)
+CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
+ Request::Flags flags,
+ const std::vector<bool>& byte_enable)
{
- // need to fill in CPU & thread IDs here
- memReq = new Request();
+ assert(byte_enable.empty() || byte_enable.size() == size);
- memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
+ Fault fault = NoFault;
+ bool checked_flags = false;
+ bool flags_match = true;
+ Addr pAddr = 0x0;
- // translate to physical address
- translateDataReadReq(memReq);
+ Addr frag_addr = addr;
+ int frag_size = 0;
+ int size_left = size;
+ bool predicate;
- Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
+ // Need to account for multiple accesses like the Atomic and TimingSimple
+ while (1) {
+ RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
+ byte_enable, frag_size,
+ size_left);
- pkt->dataStatic(&data);
+ predicate = (mem_req != nullptr);
- if (!(memReq->isUncacheable())) {
- // Access memory to see if we have the same data
- dcachePort->sendFunctional(pkt);
- } else {
- // Assume the data is correct if it's an uncached access
- memcpy(&data, &unverifiedResult.integer, sizeof(T));
- }
-
- delete pkt;
+ // translate to physical address
+ if (predicate) {
+ fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
+ }
- return NoFault;
-}
+ if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
+ flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+ mem_req->getPaddr(), mem_req->getFlags());
+ pAddr = mem_req->getPaddr();
+ checked_flags = true;
+ }
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+ // Now do the access
+ if (predicate && fault == NoFault &&
+ !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
+ PacketPtr pkt = Packet::createRead(mem_req);
-template
-Fault
-CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
+ pkt->dataStatic(data);
-template
-Fault
-CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
+ if (!(mem_req->isUncacheable() || mem_req->isLocalAccess())) {
+ // Access memory to see if we have the same data
+ dcachePort->sendFunctional(pkt);
+ } else {
+ // Assume the data is correct if it's an uncached access
+ memcpy(data, unverifiedMemData, frag_size);
+ }
-template
-Fault
-CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
+ delete pkt;
+ }
-template
-Fault
-CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
+ if (fault != NoFault) {
+ if (mem_req->isPrefetch()) {
+ fault = NoFault;
+ }
+ break;
+ }
-#endif //DOXYGEN_SHOULD_SKIP_THIS
+ //If we don't need to access a second cache line, stop now.
+ if (size_left == 0)
+ {
+ break;
+ }
-template<>
-Fault
-CheckerCPU::read(Addr addr, double &data, unsigned flags)
-{
- return read(addr, *(uint64_t*)&data, flags);
-}
+ // Setup for accessing next cache line
+ frag_addr += frag_size;
+ data += frag_size;
+ unverifiedMemData += frag_size;
+ }
-template<>
-Fault
-CheckerCPU::read(Addr addr, float &data, unsigned flags)
-{
- return read(addr, *(uint32_t*)&data, flags);
-}
+ if (!flags_match) {
+ warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
+ curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
+ unverifiedReq->getFlags(), frag_addr, pAddr, flags);
+ handleError();
+ }
-template<>
-Fault
-CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
- return read(addr, (uint32_t&)data, flags);
+ return fault;
}
-template <class T>
Fault
-CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+CheckerCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, Request::Flags flags, uint64_t *res,
+ const std::vector<bool>& byte_enable)
{
- // need to fill in CPU & thread IDs here
- memReq = new Request();
-
- memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
-
- // translate to physical address
- thread->translateDataWriteReq(memReq);
-
- // Can compare the write data and result only if it's cacheable,
- // not a store conditional, or is a store conditional that
- // succeeded.
- // @todo: Verify that actual memory matches up with these values.
- // Right now it only verifies that the instruction data is the
- // same as what was in the request that got sent to memory; there
- // is no verification that it is the same as what is in memory.
- // This is because the LSQ would have to be snooped in the CPU to
- // verify this data.
- if (unverifiedReq &&
- !(unverifiedReq->isUncacheable()) &&
- (!(unverifiedReq->isLocked()) ||
- ((unverifiedReq->isLocked()) &&
- unverifiedReq->getScResult() == 1))) {
- T inst_data;
-/*
- // This code would work if the LSQ allowed for snooping.
- Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
- pkt.dataStatic(&inst_data);
-
- dcachePort->sendFunctional(pkt);
-
- delete pkt;
-*/
- memcpy(&inst_data, unverifiedMemData, sizeof(T));
-
- if (data != inst_data) {
- warn("%lli: Store value does not match value in memory! "
- "Instruction: %#x, memory: %#x",
- curTick, inst_data, data);
- handleError();
- }
- }
-
- // Assume the result was the same as the one passed in. This checker
- // doesn't check if the SC should succeed or fail, it just checks the
- // value.
- if (res && unverifiedReq->scResultValid())
- *res = unverifiedReq->getScResult();
-
- return NoFault;
-}
+ assert(byte_enable.empty() || byte_enable.size() == size);
+ Fault fault = NoFault;
+ bool checked_flags = false;
+ bool flags_match = true;
+ Addr pAddr = 0x0;
+ static uint8_t zero_data[64] = {};
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template
-Fault
-CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
+ Addr frag_addr = addr;
+ int frag_size = 0;
+ int size_left = size;
+ bool predicate;
-template
-Fault
-CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
+ // Need to account for a multiple access like Atomic and Timing CPUs
+ while (1) {
+ RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
+ byte_enable, frag_size,
+ size_left);
-template
-Fault
-CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
-
-template
-Fault
-CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
+ predicate = (mem_req != nullptr);
-#endif //DOXYGEN_SHOULD_SKIP_THIS
+ if (predicate) {
+ fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
+ }
-template<>
-Fault
-CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint64_t*)&data, addr, flags, res);
-}
+ if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
+ flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
+ mem_req->getPaddr(), mem_req->getFlags());
+ pAddr = mem_req->getPaddr();
+ checked_flags = true;
+ }
-template<>
-Fault
-CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint32_t*)&data, addr, flags, res);
-}
+ /*
+ * We don't actually check memory for the store because there
+ * is no guarantee it has left the lsq yet, and therefore we
+ * can't verify the memory on stores without lsq snooping
+ * enabled. This is left as future work for the Checker: LSQ snooping
+ * and memory validation after stores have committed.
+ */
+ bool was_prefetch = mem_req->isPrefetch();
+
+ //If we don't need to access a second cache line, stop now.
+ if (fault != NoFault || size_left == 0)
+ {
+ if (fault != NoFault && was_prefetch) {
+ fault = NoFault;
+ }
+ break;
+ }
-template<>
-Fault
-CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write((uint32_t)data, addr, flags, res);
+ frag_addr += frag_size;
+ }
+
+ if (!flags_match) {
+ warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
+ curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
+ unverifiedReq->getFlags(), frag_addr, pAddr, flags);
+ handleError();
+ }
+
+ // Assume the result was the same as the one passed in. This checker
+ // doesn't check if the SC should succeed or fail, it just checks the
+ // value.
+ if (unverifiedReq && res && unverifiedReq->extraDataValid())
+ *res = unverifiedReq->getExtraData();
+
+ // Entire purpose here is to make sure we are getting the
+ // same data to send to the mem system as the CPU did.
+ // Cannot check this is actually what went to memory because
+ // there stores can be in ld/st queue or coherent operations
+ // overwriting values.
+ bool extraData = false;
+ if (unverifiedReq) {
+ extraData = unverifiedReq->extraDataValid() ?
+ unverifiedReq->getExtraData() : true;
+ }
+
+ // If the request is to ZERO a cache block, there is no data to check
+ // against, but it's all zero. We need something to compare to, so use a
+ // const set of zeros.
+ if (flags & Request::STORE_NO_DATA) {
+ assert(!data);
+ assert(sizeof(zero_data) <= size);
+ data = zero_data;
+ }
+
+ if (unverifiedReq && unverifiedMemData &&
+ memcmp(data, unverifiedMemData, size) && extraData) {
+ warn("%lli: Store value does not match value sent to memory! "
+ "data: %#x inst_data: %#x", curTick(), data,
+ unverifiedMemData);
+ handleError();
+ }
+
+ return fault;
}
-
-#if FULL_SYSTEM
Addr
CheckerCPU::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
+/**
+ * Checks if the flags set by the Checker and Checkee match.
+ */
bool
-CheckerCPU::translateInstReq(Request *req)
+CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
+ Addr pAddr, int flags)
{
-#if FULL_SYSTEM
- return (thread->translateInstReq(req) == NoFault);
-#else
- thread->translateInstReq(req);
- return true;
-#endif
-}
-
-void
-CheckerCPU::translateDataReadReq(Request *req)
-{
- thread->translateDataReadReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
+ Addr unverifiedVAddr = unverified_req->getVaddr();
+ Addr unverifiedPAddr = unverified_req->getPaddr();
+ int unverifiedFlags = unverified_req->getFlags();
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-void
-CheckerCPU::translateDataWriteReq(Request *req)
-{
- thread->translateDataWriteReq(req);
-
- if (req->getVaddr() != unverifiedReq->getVaddr()) {
- warn("%lli: Request virtual addresses do not match! Inst: %#x, "
- "checker: %#x",
- curTick, unverifiedReq->getVaddr(), req->getVaddr());
- handleError();
- }
- req->setPaddr(unverifiedReq->getPaddr());
-
- if (checkFlags(req)) {
- warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
- curTick, unverifiedReq->getFlags(), req->getFlags());
- handleError();
- }
-}
-
-bool
-CheckerCPU::checkFlags(Request *req)
-{
- // Remove any dynamic flags that don't have to do with the request itself.
- unsigned flags = unverifiedReq->getFlags();
- unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
- flags = flags & (mask);
- if (flags == req->getFlags()) {
+ if (unverifiedVAddr != vAddr ||
+ unverifiedPAddr != pAddr ||
+ unverifiedFlags != flags) {
return false;
- } else {
- return true;
}
+
+ return true;
}
void
CheckerCPU::dumpAndExit()
{
- warn("%lli: Checker PC:%#x, next PC:%#x",
- curTick, thread->readPC(), thread->readNextPC());
+ warn("%lli: Checker PC:%s",
+ curTick(), thread->pcState());
panic("Checker found an error!");
}
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