Merge zizzer:/bk/newmem

[gem5.git] / src / cpu / checker / cpu.hh

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 785387e600f07a74d0417f2a25d145e66913d50e..00b01171f46514aa3714eb90adb59b839418cee0 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -66,7 +66,6 @@ class ThreadContext;
 class MemInterface;
 class Checkpoint;
 class Request;
-class Sampler;
 
 /**
  * CheckerCPU class.  Dynamically verifies instructions as they are
@@ -103,6 +102,7 @@ class CheckerCPU : public BaseCPU
         Process *process;
 #endif
         bool exitOnError;
+        bool updateOnError;
         bool warnOnlyOnLoadError;
     };
 
@@ -128,6 +128,12 @@ class CheckerCPU : public BaseCPU
 
     Port *dcachePort;
 
+    virtual Port *getPort(const std::string &name, int idx)
+    {
+        panic("Not supported on checker!");
+        return NULL;
+    }
+
   public:
     // Primary thread being run.
     SimpleThread *thread;
@@ -143,7 +149,7 @@ class CheckerCPU : public BaseCPU
 
     union Result {
         uint64_t integer;
-        float fp;
+//        float fp;
         double dbl;
     };
 
@@ -165,7 +171,7 @@ class CheckerCPU : public BaseCPU
 
     virtual Counter totalInstructions() const
     {
-        return numInst - startNumInst;
+        return 0;
     }
 
     // number of simulated loads
@@ -252,7 +258,7 @@ class CheckerCPU : public BaseCPU
         thread->setFloatReg(reg_idx, val, width);
         switch(width) {
           case 32:
-            result.fp = val;
+            result.dbl = (double)val;
             break;
           case 64:
             result.dbl = val;
@@ -264,7 +270,7 @@ class CheckerCPU : public BaseCPU
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         thread->setFloatReg(reg_idx, val);
-        result.fp = val;
+        result.dbl = (double)val;
     }
 
     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
@@ -313,7 +319,7 @@ class CheckerCPU : public BaseCPU
         return thread->setMiscRegWithEffect(misc_reg, val);
     }
 
-    void recordPCChange(uint64_t val) { changedPC = true; }
+    void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
     void recordNextPCChange(uint64_t val) { changedNextPC = true; }
 
     bool translateInstReq(Request *req);
@@ -355,6 +361,7 @@ class CheckerCPU : public BaseCPU
     uint64_t newPC;
     bool changedNextPC;
     bool exitOnError;
+    bool updateOnError;
     bool warnOnlyOnLoadError;
 
     InstSeqNum youngestSN;
@@ -371,10 +378,10 @@ class Checker : public CheckerCPU
 {
   public:
     Checker(Params *p)
-        : CheckerCPU(p)
+        : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
     { }
 
-    void switchOut(Sampler *s);
+    void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
 
     void verify(DynInstPtr &inst);
@@ -388,12 +395,19 @@ class Checker : public CheckerCPU
   private:
     void handleError(DynInstPtr &inst)
     {
-        if (exitOnError)
+        if (exitOnError) {
             dumpAndExit(inst);
+        } else if (updateOnError) {
+            updateThisCycle = true;
+        }
     }
 
     void dumpAndExit(DynInstPtr &inst);
 
+    bool updateThisCycle;
+
+    DynInstPtr unverifiedInst;
+
     std::list<DynInstPtr> instList;
     typedef typename std::list<DynInstPtr>::iterator InstListIt;
     void dumpInsts();