inorder: squash on memory stall

[gem5.git] / src / cpu / checker / cpu_impl.hh

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 3bb81c4b91ca83a844baee83ec5678ebe415e43e..81f49463042416075550120a66ec04555009700e 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -32,13 +32,12 @@
 #include <string>
 
 #include "base/refcnt.hh"
+#include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/static_inst.hh"
-#include "mem/packet_impl.hh"
-#include "sim/byteswap.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
@@ -143,9 +142,9 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         // Try to fetch the instruction
 
 #if FULL_SYSTEM
-#define IFETCH_FLAGS(pc)       ((pc) & 1) ? PHYSICAL : 0
+#define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 #else
-#define IFETCH_FLAGS(pc)       0
+#define IFETCH_FLAGS(pc)        0
 #endif
 
         uint64_t fetch_PC = thread->readPC() & ~3;
@@ -154,9 +153,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         memReq = new Request(inst->threadNumber, fetch_PC,
                              sizeof(uint32_t),
                              IFETCH_FLAGS(thread->readPC()),
-                             fetch_PC, thread->readCpuId(), inst->threadNumber);
+                             fetch_PC, thread->contextId(),
+                             inst->threadNumber);
 
-        bool succeeded = translateInstReq(memReq);
+        bool succeeded = itb->translateAtomic(memReq, thread);
 
         if (!succeeded) {
             if (inst->getFault() == NoFault) {
@@ -183,7 +183,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         }
 
         if (fault == NoFault) {
-            Packet *pkt = new Packet(memReq, Packet::ReadReq,
+            PacketPtr pkt = new Packet(memReq, Packet::ReadReq,
                                      Packet::Broadcast);
 
             pkt->dataStatic(&machInst);
@@ -201,8 +201,13 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
             // Checks both the machine instruction and the PC.
             validateInst(inst);
 
+#if THE_ISA == ALPHA_ISA
             curStaticInst = StaticInst::decode(makeExtMI(machInst,
                                                          thread->readPC()));
+#elif THE_ISA == SPARC_ISA
+            curStaticInst = StaticInst::decode(makeExtMI(machInst,
+                                                         thread->getTC()));
+#endif
 
 #if FULL_SYSTEM
             thread->setInst(machInst);
@@ -383,13 +388,13 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
         int misc_reg_idx = miscRegIdxs.front();
         miscRegIdxs.pop();
 
-        if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
-            thread->readMiscReg(misc_reg_idx)) {
+        if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
+            thread->readMiscRegNoEffect(misc_reg_idx)) {
             warn("%lli: Misc reg idx %i (side effect) does not match! "
                  "Inst: %#x, checker: %#x",
                  curTick, misc_reg_idx,
-                 inst->tcBase()->readMiscReg(misc_reg_idx),
-                 thread->readMiscReg(misc_reg_idx));
+                 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
+                 thread->readMiscRegNoEffect(misc_reg_idx));
             handleError(inst);
         }
     }
@@ -403,19 +408,20 @@ Checker<DynInstPtr>::validateState()
         warn("%lli: Instruction PC %#x results didn't match up, copying all "
              "registers from main CPU", curTick, unverifiedInst->readPC());
         // Heavy-weight copying of all registers
-        cpuXC->copyArchRegs(unverifiedInst->xcBase());
+        thread->copyArchRegs(unverifiedInst->tcBase());
         // Also advance the PC.  Hopefully no PC-based events happened.
 #if THE_ISA != MIPS_ISA
         // go to the next instruction
-        cpuXC->setPC(cpuXC->readNextPC());
-        cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+        thread->setPC(thread->readNextPC());
+        thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 #else
         // go to the next instruction
-        cpuXC->setPC(cpuXC->readNextPC());
-        cpuXC->setNextPC(cpuXC->readNextNPC());
-        cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+        thread->setPC(thread->readNextPC());
+        thread->setNextPC(thread->readNextNPC());
+        thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 #endif
         updateThisCycle = false;
+    }
 }
 
 template <class DynInstPtr>
@@ -428,7 +434,7 @@ Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
     } else if (idx < TheISA::Fpcr_DepTag) {
         thread->setFloatRegBits(idx, inst->readIntResult());
     } else {
-        thread->setMiscReg(idx, inst->readIntResult());
+        thread->setMiscRegNoEffect(idx, inst->readIntResult());
     }
 }