cpu: add a condition-code register class

[gem5.git] / src / cpu / checker / cpu_impl.hh

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 40f1cef6ad4aad98b36e453329de4ad1706d9cf3..e18644e0edd6c7071d01ad815bae5c4a0f971a99 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,6 +51,7 @@
 #include "config/the_isa.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
@@ -306,7 +308,6 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                     StaticInstPtr instPtr = NULL;
 
                     //Predecode, ie bundle up an ExtMachInst
-                    thread->decoder.setTC(thread->getTC());
                     //If more fetch data is needed, pass it in.
                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
@@ -574,12 +575,12 @@ Checker<Impl>::validateState()
              "registers from main CPU", curTick(), unverifiedInst->instAddr());
 
         // Terribly convoluted way to make sure O3 model does not implode
-        bool inSyscall = unverifiedInst->thread->inSyscall;
-        unverifiedInst->thread->inSyscall = true;
+        bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
+        unverifiedInst->thread->noSquashFromTC = true;
 
         // Heavy-weight copying of all registers
         thread->copyArchRegs(unverifiedInst->tcBase());
-        unverifiedInst->thread->inSyscall = inSyscall;
+        unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
 
         // Set curStaticInst to unverifiedInst->staticInst
         curStaticInst = unverifiedInst->staticInst;
@@ -598,13 +599,20 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
     // so do the fix-up then start with the next dest reg;
     if (start_idx >= 0) {
         RegIndex idx = inst->destRegIdx(start_idx);
-        if (idx < TheISA::FP_Base_DepTag) {
+        switch (regIdxToClass(idx)) {
+          case IntRegClass:
             thread->setIntReg(idx, mismatch_val);
-        } else if (idx < TheISA::Ctrl_Base_DepTag) {
+            break;
+          case FloatRegClass:
             thread->setFloatRegBits(idx, mismatch_val);
-        } else if (idx < TheISA::Max_DepTag) {
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag,
+            break;
+          case CCRegClass:
+            thread->setCCReg(idx, mismatch_val);
+            break;
+          case MiscRegClass:
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
                                mismatch_val);
+            break;
         }
     }
     start_idx++;
@@ -612,14 +620,22 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val,
     for (int i = start_idx; i < inst->numDestRegs(); i++) {
         RegIndex idx = inst->destRegIdx(i);
         inst->template popResult<uint64_t>(res);
-        if (idx < TheISA::FP_Base_DepTag) {
+        switch (regIdxToClass(idx)) {
+          case IntRegClass:
             thread->setIntReg(idx, res);
-        } else if (idx < TheISA::Ctrl_Base_DepTag) {
+            break;
+          case FloatRegClass:
             thread->setFloatRegBits(idx, res);
-        } else if (idx < TheISA::Max_DepTag) {
+            break;
+          case CCRegClass:
+            thread->setCCReg(idx, res);
+            break;
+          case MiscRegClass:
             // Try to get the proper misc register index for ARM here...
-            thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res);
-        } // else Register is out of range...
+            thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res);
+            break;
+            // else Register is out of range...
+        }
     }
 }