/*
+ * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
#include "arch/types.hh"
+#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
+#include "debug/Checker.hh"
class EndQuiesceEvent;
-namespace Kernel {
- class Statistics;
+namespace TheISA {
+ namespace Kernel {
+ class Statistics;
+ };
+ class Decoder;
};
/**
BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
- void setCpuId(int id)
+ uint32_t socketId() const { return actualTC->socketId(); }
+
+ int cpuId() const { return actualTC->cpuId(); }
+
+ ContextID contextId() const { return actualTC->contextId(); }
+
+ void setContextId(ContextID id)
+ {
+ actualTC->setContextId(id);
+ checkerTC->setContextId(id);
+ }
+
+ /** Returns this thread's ID number. */
+ int threadId() const { return actualTC->threadId(); }
+ void setThreadId(int id)
{
- actualTC->setCpuId(id);
- checkerTC->setCpuId(id);
+ checkerTC->setThreadId(id);
+ actualTC->setThreadId(id);
}
- int readCpuId() { return actualTC->readCpuId(); }
+ TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
+
+ TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+
+ CheckerCPU *getCheckerCpuPtr()
+ {
+ return checkerCPU;
+ }
+
+ TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
-#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
- PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
+ TheISA::Kernel::Statistics *getKernelStats()
+ { return actualTC->getKernelStats(); }
- AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
+ Process *getProcessPtr() { return actualTC->getProcessPtr(); }
- AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
- Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+ FSTranslatingPortProxy &getVirtProxy()
+ { return actualTC->getVirtProxy(); }
- FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+ void initMemProxies(ThreadContext *tc)
+ { actualTC->initMemProxies(tc); }
- VirtualPort *getVirtPort(ThreadContext *tc = NULL)
- { return actualTC->getVirtPort(); }
+ void connectMemPorts(ThreadContext *tc)
+ {
+ actualTC->connectMemPorts(tc);
+ }
- void delVirtPort(VirtualPort *vp) { actualTC->delVirtPort(vp); }
-#else
- TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+ SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
- Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
+ /** Executes a syscall in SE mode. */
+ void syscall(int64_t callnum, Fault *fault)
+ { return actualTC->syscall(callnum, fault); }
Status status() const { return actualTC->status(); }
checkerTC->setStatus(new_status);
}
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualTC->activate(delay); }
+ /// Set the status to Active.
+ void activate() { actualTC->activate(); }
/// Set the status to Suspended.
void suspend() { actualTC->suspend(); }
- /// Set the status to Unallocated.
- void deallocate(int delay = 0) { actualTC->deallocate(delay); }
-
/// Set the status to Halted.
void halt() { actualTC->halt(); }
-#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
void takeOverFrom(ThreadContext *oldContext)
{
checkerTC->copyState(oldContext);
}
- void regStats(const std::string &name) { actualTC->regStats(name); }
-
- void serialize(std::ostream &os) { actualTC->serialize(os); }
- void unserialize(Checkpoint *cp, const std::string §ion)
- { actualTC->unserialize(cp, section); }
+ void regStats(const std::string &name)
+ {
+ actualTC->regStats(name);
+ checkerTC->regStats(name);
+ }
-#if FULL_SYSTEM
EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
Tick readLastActivate() { return actualTC->readLastActivate(); }
void profileClear() { return actualTC->profileClear(); }
void profileSample() { return actualTC->profileSample(); }
-#endif
-
- int getThreadNum() { return actualTC->getThreadNum(); }
-
- // @todo: Do I need this?
- MachInst getInst() { return actualTC->getInst(); }
// @todo: Do I need this?
void copyArchRegs(ThreadContext *tc)
uint64_t readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatReg readFloatReg(int reg_idx, int width)
- { return actualTC->readFloatReg(reg_idx, width); }
-
FloatReg readFloatReg(int reg_idx)
{ return actualTC->readFloatReg(reg_idx); }
- FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualTC->readFloatRegBits(reg_idx, width); }
-
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
+ CCReg readCCReg(int reg_idx)
+ { return actualTC->readCCReg(reg_idx); }
+
void setIntReg(int reg_idx, uint64_t val)
{
actualTC->setIntReg(reg_idx, val);
checkerTC->setIntReg(reg_idx, val);
}
- void setFloatReg(int reg_idx, FloatReg val, int width)
- {
- actualTC->setFloatReg(reg_idx, val, width);
- checkerTC->setFloatReg(reg_idx, val, width);
- }
-
void setFloatReg(int reg_idx, FloatReg val)
{
actualTC->setFloatReg(reg_idx, val);
checkerTC->setFloatReg(reg_idx, val);
}
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
- {
- actualTC->setFloatRegBits(reg_idx, val, width);
- checkerTC->setFloatRegBits(reg_idx, val, width);
- }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
actualTC->setFloatRegBits(reg_idx, val);
checkerTC->setFloatRegBits(reg_idx, val);
}
- uint64_t readPC() { return actualTC->readPC(); }
-
- void setPC(uint64_t val)
+ void setCCReg(int reg_idx, CCReg val)
{
- actualTC->setPC(val);
- checkerTC->setPC(val);
- checkerCPU->recordPCChange(val);
+ actualTC->setCCReg(reg_idx, val);
+ checkerTC->setCCReg(reg_idx, val);
}
- uint64_t readNextPC() { return actualTC->readNextPC(); }
+ /** Reads this thread's PC state. */
+ TheISA::PCState pcState()
+ { return actualTC->pcState(); }
- void setNextPC(uint64_t val)
+ /** Sets this thread's PC state. */
+ void pcState(const TheISA::PCState &val)
{
- actualTC->setNextPC(val);
- checkerTC->setNextPC(val);
- checkerCPU->recordNextPCChange(val);
+ DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
+ val, checkerTC->pcState());
+ checkerTC->pcState(val);
+ checkerCPU->recordPCChange(val);
+ return actualTC->pcState(val);
}
- uint64_t readNextNPC() { return actualTC->readNextNPC(); }
-
- void setNextNPC(uint64_t val)
+ void pcStateNoRecord(const TheISA::PCState &val)
{
- actualTC->setNextNPC(val);
- checkerTC->setNextNPC(val);
- checkerCPU->recordNextPCChange(val);
+ return actualTC->pcState(val);
}
+ /** Reads this thread's PC. */
+ Addr instAddr()
+ { return actualTC->instAddr(); }
+
+ /** Reads this thread's next PC. */
+ Addr nextInstAddr()
+ { return actualTC->nextInstAddr(); }
+
+ /** Reads this thread's next PC. */
+ MicroPC microPC()
+ { return actualTC->microPC(); }
+
+ MiscReg readMiscRegNoEffect(int misc_reg) const
+ { return actualTC->readMiscRegNoEffect(misc_reg); }
+
MiscReg readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
- { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
-
- Fault setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
- checkerTC->setMiscReg(misc_reg, val);
- return actualTC->setMiscReg(misc_reg, val);
+ DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
+ " and O3..\n", misc_reg);
+ checkerTC->setMiscRegNoEffect(misc_reg, val);
+ actualTC->setMiscRegNoEffect(misc_reg, val);
}
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val)
{
- checkerTC->setMiscRegWithEffect(misc_reg, val);
- return actualTC->setMiscRegWithEffect(misc_reg, val);
+ DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
+ " and O3..\n", misc_reg);
+ checkerTC->setMiscReg(misc_reg, val);
+ actualTC->setMiscReg(misc_reg, val);
}
+ int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
+ int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
+ int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
void setStCondFailures(unsigned sc_failures)
{
- checkerTC->setStCondFailures(sc_failures);
actualTC->setStCondFailures(sc_failures);
}
-#if FULL_SYSTEM
- bool inPalMode() { return actualTC->inPalMode(); }
-#endif
- // @todo: Fix this!
- bool misspeculating() { return actualTC->misspeculating(); }
+ Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
+ uint64_t readIntRegFlat(int idx)
+ { return actualTC->readIntRegFlat(idx); }
- // used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
- {
- checkerTC->setSyscallArg(i, val);
- actualTC->setSyscallArg(i, val);
- }
+ void setIntRegFlat(int idx, uint64_t val)
+ { actualTC->setIntRegFlat(idx, val); }
- void setSyscallReturn(SyscallReturn return_value)
- {
- checkerTC->setSyscallReturn(return_value);
- actualTC->setSyscallReturn(return_value);
- }
+ FloatReg readFloatRegFlat(int idx)
+ { return actualTC->readFloatRegFlat(idx); }
- Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- actualTC->changeRegFileContext(param, val);
- checkerTC->changeRegFileContext(param, val);
- }
+ void setFloatRegFlat(int idx, FloatReg val)
+ { actualTC->setFloatRegFlat(idx, val); }
+
+ FloatRegBits readFloatRegBitsFlat(int idx)
+ { return actualTC->readFloatRegBitsFlat(idx); }
+
+ void setFloatRegBitsFlat(int idx, FloatRegBits val)
+ { actualTC->setFloatRegBitsFlat(idx, val); }
+
+ CCReg readCCRegFlat(int idx)
+ { return actualTC->readCCRegFlat(idx); }
+
+ void setCCRegFlat(int idx, CCReg val)
+ { actualTC->setCCRegFlat(idx, val); }
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
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