A possible implementation of a multiplexed bus.

[gem5.git] / src / cpu / cpu_models.py

diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py
index ccaceeff3eb1d3c9e9faf145f9a63c9aceb209a8..5b0c6c4dac12140effd383fecba23ab830f7bb46 100644 (file)
--- a/src/cpu/cpu_models.py
+++ b/src/cpu/cpu_models.py
@@ -80,5 +80,5 @@ CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
          '#include "cpu/checker/cpu.hh"',
          { 'CPU_exec_context': 'CheckerCPU' })
 CpuModel('O3CPU', 'o3_cpu_exec.cc',
-         '#include "cpu/o3/alpha/dyn_inst.hh"',
-         { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
+         '#include "cpu/o3/isa_specific.hh"',
+         { 'CPU_exec_context': 'O3DynInst' })