Fix bug when blocking due to no free registers.

[gem5.git] / src / cpu / exec_context.hh

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 13f70fa794d01513e9fa520ad0a9d805225b71dc..2b9fe4bcf11dbda86990f85be8c7b604041a8d59 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -48,39 +48,42 @@ class ExecContext {
     // to do).
 
     /** Reads an integer register. */
-    uint64_t readIntReg(const StaticInst *si, int idx);
+    uint64_t readIntRegOperand(const StaticInst *si, int idx);
 
     /** Reads a floating point register of a specific width. */
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width);
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
 
     /** Reads a floating point register of single register width. */
-    FloatReg readFloatReg(const StaticInst *si, int idx);
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx);
 
     /** Reads a floating point register of a specific width in its
      * binary format, instead of by value. */
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+                                         int width);
 
     /** Reads a floating point register in its binary format, instead
      * of by value. */
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
 
     /** Sets an integer register to a value. */
-    void setIntReg(const StaticInst *si, int idx, uint64_t val);
+    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
 
     /** Sets a floating point register of a specific width to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+                            int width);
 
     /** Sets a floating point register of single width to a value. */
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val);
+    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
 
     /** Sets the bits of a floating point register of a specific width
      * to a binary value. */
-    void setFloatRegBits(const StaticInst *si, int idx,
-                         FloatRegBits val, int width);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val, int width);
 
     /** Sets the bits of a floating point register of single width
      * to a binary value. */
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
+    void setFloatRegOperandBits(const StaticInst *si, int idx,
+                                FloatRegBits val);
 
     /** Reads the PC. */
     uint64_t readPC();
@@ -97,18 +100,18 @@ class ExecContext {
     void setNextNPC(uint64_t val);
 
     /** Reads a miscellaneous register. */
-    MiscReg readMiscReg(int misc_reg);
+    MiscReg readMiscRegNoEffect(int misc_reg);
 
     /** Reads a miscellaneous register, handling any architectural
      * side effects due to reading that register. */
-    MiscReg readMiscRegWithEffect(int misc_reg);
+    MiscReg readMiscReg(int misc_reg);
 
     /** Sets a miscellaneous register. */
-    void setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 
     /** Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register. */
-    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Records the effective address of the instruction.  Only valid
      * for memory ops. */