* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ * Nathan Binkert
*/
#ifndef __EXETRACE_HH__
#include "sim/host.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
-class BaseCPU;
+class ThreadContext;
namespace Trace {
// The following fields are initialized by the constructor and
// thus guaranteed to be valid.
- BaseCPU *cpu;
+ ThreadContext *thread;
// need to make this ref-counted so it doesn't go away before we
// dump the record
StaticInstPtr staticInst;
Addr PC;
bool misspeculating;
- unsigned thread;
// The remaining fields are only valid for particular instruction
// types (e.g, addresses for memory ops) or when particular
bool regs_valid;
public:
- InstRecord(Tick _cycle, BaseCPU *_cpu,
+ InstRecord(Tick _cycle, ThreadContext *_thread,
const StaticInstPtr &_staticInst,
- Addr _pc, bool spec, int _thread)
- : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
- misspeculating(spec), thread(_thread)
+ Addr _pc, bool spec)
+ : Record(_cycle), thread(_thread),
+ staticInst(_staticInst), PC(_pc),
+ misspeculating(spec)
{
data_status = DataInvalid;
addr_valid = false;
PRINT_INT_REGS,
PRINT_FETCH_SEQ,
PRINT_CP_SEQ,
+ PRINT_REG_DELTA,
+ PC_SYMBOL,
INTEL_FORMAT,
NUM_BITS
};
inline
InstRecord *
-getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
+getInstRecord(Tick cycle, ThreadContext *tc,
const StaticInstPtr staticInst,
- Addr pc, int thread = 0)
+ Addr pc)
{
if (DTRACE(InstExec) &&
- (InstRecord::traceMisspec() || !xc->misspeculating())) {
- return new InstRecord(cycle, cpu, staticInst, pc,
- xc->misspeculating(), thread);
+ (InstRecord::traceMisspec() || !tc->misspeculating())) {
+ return new InstRecord(cycle, tc, staticInst, pc,
+ tc->misspeculating());
}
return NULL;