Merge in .hgignore from head.

[gem5.git] / src / cpu / exetrace.hh

diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index d31e99c4a28c818f6ae247d1c7efa9250c7bb6ee..8c0fa22cb401aa825d6697d04c8245064e5d2c5f 100644 (file)
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -32,34 +32,36 @@
 #ifndef __EXETRACE_HH__
 #define __EXETRACE_HH__
 
+#include <cstring>
 #include <fstream>
 #include <vector>
 
-#include "sim/host.hh"
-#include "cpu/inst_seq.hh"     // for InstSeqNum
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/inst_seq.hh"     // for InstSeqNum
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "sim/host.hh"
 
-class BaseCPU;
+class ThreadContext;
 
 
 namespace Trace {
 
-class InstRecord : public Record
+class InstRecord
 {
   protected:
     typedef TheISA::IntRegFile IntRegFile;
 
+    Tick when;
+
     // The following fields are initialized by the constructor and
     // thus guaranteed to be valid.
-    BaseCPU *cpu;
+    ThreadContext *thread;
     // need to make this ref-counted so it doesn't go away before we
     // dump the record
     StaticInstPtr staticInst;
     Addr PC;
     bool misspeculating;
-    unsigned thread;
 
     // The remaining fields are only valid for particular instruction
     // types (e.g, addresses for memory ops) or when particular
@@ -95,11 +97,12 @@ class InstRecord : public Record
     bool regs_valid;
 
   public:
-    InstRecord(Tick _cycle, BaseCPU *_cpu,
+    InstRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr &_staticInst,
-               Addr _pc, bool spec, int _thread)
-        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
-          misspeculating(spec), thread(_thread)
+               Addr _pc, bool spec)
+        : when(_when), thread(_thread),
+          staticInst(_staticInst), PC(_pc),
+          misspeculating(spec)
     {
         data_status = DataInvalid;
         addr_valid = false;
@@ -109,12 +112,12 @@ class InstRecord : public Record
         cp_seq_valid = false;
     }
 
-    virtual ~InstRecord() { }
-
-    virtual void dump(std::ostream &outs);
+    ~InstRecord() { }
 
     void setAddr(Addr a) { addr = a; addr_valid = true; }
 
+    void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
+    void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
     void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
     void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
     void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
@@ -135,29 +138,7 @@ class InstRecord : public Record
 
     void setRegs(const IntRegFile &regs);
 
-    void finalize() { theLog.append(this); }
-
-    enum InstExecFlagBits {
-        TRACE_MISSPEC = 0,
-        PRINT_CYCLE,
-        PRINT_OP_CLASS,
-        PRINT_THREAD_NUM,
-        PRINT_RESULT_DATA,
-        PRINT_EFF_ADDR,
-        PRINT_INT_REGS,
-        PRINT_FETCH_SEQ,
-        PRINT_CP_SEQ,
-        PC_SYMBOL,
-        INTEL_FORMAT,
-        NUM_BITS
-    };
-
-    static std::vector<bool> flags;
-    static std::string trace_system;
-
-    static void setParams();
-
-    static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
+    void dump();
 };
 
 
@@ -167,26 +148,26 @@ InstRecord::setRegs(const IntRegFile &regs)
     if (!iregs)
       iregs = new iRegFile;
 
-    memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
+    std::memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
     regs_valid = true;
 }
 
-inline
-InstRecord *
-getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
-              const StaticInstPtr staticInst,
-              Addr pc, int thread = 0)
+inline InstRecord *
+getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
+              Addr pc)
 {
-    if (DTRACE(InstExec) &&
-        (InstRecord::traceMisspec() || !xc->misspeculating())) {
-        return new InstRecord(cycle, cpu, staticInst, pc,
-                              xc->misspeculating(), thread);
-    }
+    if (!IsOn(ExecEnable))
+        return NULL;
 
-    return NULL;
-}
+    if (!Trace::enabled)
+        return NULL;
 
+    if (!IsOn(ExecSpeculative) && tc->misspeculating())
+        return NULL;
 
+    return new InstRecord(when, tc, staticInst, pc, tc->misspeculating());
 }
 
+/* namespace Trace */ }
+
 #endif // __EXETRACE_HH__