Yet another merge with the main repository.

[gem5.git] / src / cpu / inorder / InOrderCPU.py

diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 9faadc68cb2b64bb785c08536ba0fa12a72b6710..40af48b1922ff303ad08bf2a43160500db0274ea 100644 (file)
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -28,21 +28,25 @@
 
 from m5.params import *
 from m5.proxy import *
-from m5 import build_env
 from BaseCPU import BaseCPU
 
+class ThreadModel(Enum):
+    vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
+
 class InOrderCPU(BaseCPU):
     type = 'InOrderCPU'
     activity = Param.Unsigned(0, "Initial count")
 
+    threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
+    
     cachePorts = Param.Unsigned(2, "Cache Ports")
-    stageWidth = Param.Unsigned(1, "Stage width")
+    stageWidth = Param.Unsigned(4, "Stage width")
 
     fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from")
     dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
-    icache_port = Port("Instruction Port")
-    dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+
+    fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
+    memBlockSize = Param.Unsigned(64, "Memory Block Size")
 
     predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
     localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
@@ -65,8 +69,6 @@ class InOrderCPU(BaseCPU):
     functionTraceStart = Param.Tick(0, "Cycle to start function trace")
     stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
 
-    memBlockSize = Param.Unsigned(64, "Memory Block Size")
-
     multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
     multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
     div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations")