from m5.params import *
from m5.proxy import *
from BaseCPU import BaseCPU
+from BranchPredictor import BranchPredictor
class ThreadModel(Enum):
vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
+ cxx_header = "cpu/inorder/cpu.hh"
activity = Param.Unsigned(0, "Initial count")
+ @classmethod
+ def memory_mode(cls):
+ return 'timing'
+
+ @classmethod
+ def require_caches(cls):
+ return True
+
+ @classmethod
+ def support_take_over(cls):
+ return True
+
threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
cachePorts = Param.Unsigned(2, "Cache Ports")
stageWidth = Param.Unsigned(4, "Stage width")
- fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from")
- dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _cached_ports = ['icache_port', 'dcache_port']
-
- predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
- localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
- localCtrBits = Param.Unsigned(2, "Bits per counter")
- localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
- localHistoryBits = Param.Unsigned(11, "Bits for the local history")
- globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
- globalCtrBits = Param.Unsigned(2, "Bits per counter")
- globalHistoryBits = Param.Unsigned(13, "Bits of history")
- choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
- choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
-
- BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
- BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
-
- RASSize = Param.Unsigned(16, "RAS size")
+ fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
+ memBlockSize = Param.Unsigned(64, "Memory Block Size")
- instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
- functionTrace = Param.Bool(False, "Enable function trace")
- functionTraceStart = Param.Tick(0, "Cycle to start function trace")
stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
- memBlockSize = Param.Unsigned(64, "Memory Block Size")
+ multLatency = Param.Cycles(1, "Latency for Multiply Operations")
+ multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations")
+ div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations")
+ div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations")
+ div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations")
+ div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations")
+ div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations")
+ div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations")
+ div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
+ div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
- multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
- multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
- div8Latency = Param.Unsigned(1, "Latency for 8-bit Divide Operations")
- div8RepeatRate = Param.Unsigned(1, "Repeat Rate for 8-bit Divide Operations")
- div16Latency = Param.Unsigned(1, "Latency for 16-bit Divide Operations")
- div16RepeatRate = Param.Unsigned(1, "Repeat Rate for 16-bit Divide Operations")
- div24Latency = Param.Unsigned(1, "Latency for 24-bit Divide Operations")
- div24RepeatRate = Param.Unsigned(1, "Repeat Rate for 24-bit Divide Operations")
- div32Latency = Param.Unsigned(1, "Latency for 32-bit Divide Operations")
- div32RepeatRate = Param.Unsigned(1, "Repeat Rate for 32-bit Divide Operations")
+ branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+ Parent.numThreads),
+ "Branch Predictor")