cpu: Update DRAM traffic gen

[gem5.git] / src / cpu / inorder / InOrderCPU.py

diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index e29a29556bc6d10e658b45930698d2bc5b6bb6b1..920b9cdc13bedca9714f9cff2520f40585f74c2c 100644 (file)
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -47,6 +47,10 @@ class InOrderCPU(BaseCPU):
     def require_caches(cls):
         return True
 
+    @classmethod
+    def support_take_over(cls):
+        return True
+
     threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
     
     cachePorts = Param.Unsigned(2, "Cache Ports")
@@ -68,4 +72,6 @@ class InOrderCPU(BaseCPU):
     div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
     div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
 
-    branchPred = BranchPredictor(numThreads = Parent.numThreads)
+    branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
+                                                       Parent.numThreads),
+                                       "Branch Predictor")