Import('*')
if 'InOrderCPU' in env['CPU_MODELS']:
- SimObject('InOrderCPU.py')
- SimObject('InOrderTrace.py')
+ SimObject('InOrderCPU.py')
+ SimObject('InOrderTrace.py')
- TraceFlag('ResReqCount')
- TraceFlag('InOrderStage')
- TraceFlag('InOrderStall')
- TraceFlag('InOrderCPU')
- TraceFlag('RegDepMap')
- TraceFlag('InOrderDynInst')
- TraceFlag('Resource')
- TraceFlag('InOrderAGEN')
- TraceFlag('InOrderFetchSeq')
- TraceFlag('InOrderTLB')
- TraceFlag('InOrderCachePort')
- TraceFlag('InOrderBPred')
- TraceFlag('InOrderDecode')
- TraceFlag('InOrderExecute')
- TraceFlag('InOrderInstBuffer')
- TraceFlag('InOrderUseDef')
- TraceFlag('InOrderMDU')
- TraceFlag('InOrderGraduation')
- TraceFlag('RefCount')
+ DebugFlag('ResReqCount')
+ DebugFlag('InOrderStage')
+ DebugFlag('InOrderStall')
+ DebugFlag('InOrderCPU')
+ DebugFlag('RegDepMap')
+ DebugFlag('InOrderDynInst')
+ DebugFlag('Resource')
+ DebugFlag('InOrderAGEN')
+ DebugFlag('InOrderFetchSeq')
+ DebugFlag('InOrderTLB')
+ DebugFlag('InOrderCachePort')
+ DebugFlag('InOrderBPred')
+ DebugFlag('InOrderDecode')
+ DebugFlag('InOrderExecute')
+ DebugFlag('InOrderInstBuffer')
+ DebugFlag('InOrderUseDef')
+ DebugFlag('InOrderMDU')
+ DebugFlag('InOrderGraduation')
+ DebugFlag('ThreadModel')
+ DebugFlag('RefCount')
+ DebugFlag('AddrDep')
+ DebugFlag('SkedCache')
- CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
- 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
- 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
- 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource'])
+ CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
+ 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
+ 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
+ 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
+ 'InOrderStall','ThreadModel', 'AddrDep'])
- Source('pipeline_traits.cc')
- Source('inorder_dyn_inst.cc')
- Source('inorder_cpu_builder.cc')
- Source('inorder_trace.cc')
- Source('pipeline_stage.cc')
- Source('first_stage.cc')
- Source('resource.cc')
- Source('resources/agen_unit.cc')
- Source('resources/execution_unit.cc')
- Source('resources/bpred_unit.cc')
- Source('resources/branch_predictor.cc')
- Source('resources/cache_unit.cc')
- Source('resources/use_def.cc')
- Source('resources/decode_unit.cc')
- Source('resources/inst_buffer.cc')
- Source('resources/graduation_unit.cc')
- Source('resources/tlb_unit.cc')
- Source('resources/fetch_seq_unit.cc')
- Source('resources/mult_div_unit.cc')
- Source('resource_pool.cc')
- Source('reg_dep_map.cc')
- Source('thread_context.cc')
- Source('cpu.cc')
+ Source('inorder_dyn_inst.cc')
+ Source('inorder_cpu_builder.cc')
+ Source('inorder_trace.cc')
+ Source('pipeline_stage.cc')
+ Source('first_stage.cc')
+ Source('resource.cc')
+ Source('resources/agen_unit.cc')
+ Source('resources/execution_unit.cc')
+ Source('resources/bpred_unit.cc')
+ Source('resources/branch_predictor.cc')
+ Source('resources/cache_unit.cc')
+ Source('resources/fetch_unit.cc')
+ Source('resources/use_def.cc')
+ Source('resources/decode_unit.cc')
+ Source('resources/inst_buffer.cc')
+ Source('resources/graduation_unit.cc')
+ Source('resources/fetch_seq_unit.cc')
+ Source('resources/mult_div_unit.cc')
+ Source('resource_pool.cc')
+ Source('resource_sked.cc')
+ Source('reg_dep_map.cc')
+ Source('thread_state.cc')
+ Source('thread_context.cc')
+ Source('cpu.cc')