arch, cpu: Add support for flattening misc register indexes.

[gem5.git] / src / cpu / inorder / cpu.hh

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 615d0eb90a24b289722120211bc8186be580fd1f..1183f6fc9ab29876b2b80fd653a132c6978d5504 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -1,5 +1,6 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -65,6 +66,7 @@
 #include "cpu/o3/rename_map.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/timebuf.hh"
 #include "mem/packet.hh"
@@ -91,6 +93,7 @@ class InOrderCPU : public BaseCPU
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
+    typedef TheISA::CCReg CCReg;
     typedef TheISA::MiscReg MiscReg;
     typedef TheISA::RegIndex RegIndex;
 
@@ -109,11 +112,13 @@ class InOrderCPU : public BaseCPU
     /* Destructor */
     ~InOrderCPU();
     
+    void verifyMemoryMode() const;
+
     /** Return a reference to the data port. */
-    virtual CpuPort &getDataPort() { return dataPort; }
+    virtual MasterPort &getDataPort() { return dataPort; }
 
     /** Return a reference to the instruction port. */
-    virtual CpuPort &getInstPort() { return instPort; }
+    virtual MasterPort &getInstPort() { return instPort; }
 
     /** CPU ID */
     int cpu_id;
@@ -156,7 +161,7 @@ class InOrderCPU : public BaseCPU
      * CachePort class for the in-order CPU, interacting with a
      * specific CacheUnit in the pipeline.
      */
-    class CachePort : public CpuPort
+    class CachePort : public MasterPort
     {
 
       private:
@@ -165,7 +170,7 @@ class InOrderCPU : public BaseCPU
 
       public:
         /** Default constructor. */
-        CachePort(CacheUnit *_cacheUnit);
+        CachePort(CacheUnit *_cacheUnit, const std::string& name);
 
       protected:
 
@@ -201,10 +206,10 @@ class InOrderCPU : public BaseCPU
     TickEvent tickEvent;
 
     /** Schedule tick event, regardless of its current state. */
-    void scheduleTickEvent(int delay)
+    void scheduleTickEvent(Cycles delay)
     {
         assert(!tickEvent.scheduled() || tickEvent.squashed());
-        reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
+        reschedule(&tickEvent, clockEdge(delay), true);
     }
 
     /** Unschedule tick event, regardless of its current state. */
@@ -279,7 +284,7 @@ class InOrderCPU : public BaseCPU
         const char *description() const;
 
         /** Schedule Event */
-        void scheduleEvent(int delay);
+        void scheduleEvent(Cycles delay);
 
         /** Unschedule This Event */
         void unscheduleEvent();
@@ -287,7 +292,7 @@ class InOrderCPU : public BaseCPU
 
     /** Schedule a CPU Event */
     void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
-                          DynInstPtr inst, unsigned delay = 0,
+                          DynInstPtr inst, Cycles delay = Cycles(0),
                           CPUEventPri event_pri = InOrderCPU_Pri);
 
   public:
@@ -323,16 +328,16 @@ class InOrderCPU : public BaseCPU
         FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs];
     } floatRegs;
     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
+#ifdef ISA_HAS_CC_REGS
+    TheISA::CCReg ccRegs[ThePipeline::MaxThreads][TheISA::NumCCRegs];
+#endif
 
     /** ISA state */
-    TheISA::ISA isa[ThePipeline::MaxThreads];
+    std::vector<TheISA::ISA *> isa;
 
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
 
-    /** Register Types Used in Dependency Tracking */
-    enum RegType { IntType, FloatType, MiscType, NumRegTypes};
-
     /** Global communication structure */
     TimeBuffer<TimeStruct> timeBuffer;
 
@@ -479,19 +484,20 @@ class InOrderCPU : public BaseCPU
 
     /** Schedule a syscall on the CPU */
     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
-                        int delay = 0);
+                        Cycles delay = Cycles(0));
 
     /** Executes a syscall.*/
     void syscall(int64_t callnum, ThreadID tid);
 
     /** Schedule a trap on the CPU */
-    void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
+    void trapContext(Fault fault, ThreadID tid, DynInstPtr inst,
+                     Cycles delay = Cycles(0));
 
     /** Perform trap to Handle Given Fault */
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
     /** Schedule thread activation on the CPU */
-    void activateContext(ThreadID tid, int delay = 0);
+    void activateContext(ThreadID tid, Cycles delay = Cycles(0));
 
     /** Add Thread to Active Threads List. */
     void activateThread(ThreadID tid);
@@ -500,13 +506,13 @@ class InOrderCPU : public BaseCPU
     void activateThreadInPipeline(ThreadID tid);
     
     /** Schedule Thread Activation from Ready List */
-    void activateNextReadyContext(int delay = 0);
+    void activateNextReadyContext(Cycles delay = Cycles(0));
 
     /** Add Thread From Ready List to Active Threads List. */
     void activateNextReadyThread();
 
     /** Schedule a thread deactivation on the CPU */
-    void deactivateContext(ThreadID tid, int delay = 0);
+    void deactivateContext(ThreadID tid, Cycles delay = Cycles(0));
 
     /** Remove from Active Thread List */
     void deactivateThread(ThreadID tid);
@@ -529,7 +535,8 @@ class InOrderCPU : public BaseCPU
      *  squashDueToMemStall() - squashes pipeline
      *  @note: maybe squashContext/squashThread would be better?
      */
-    void squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay = 0);
+    void squashFromMemStall(DynInstPtr inst, ThreadID tid,
+                            Cycles delay = Cycles(0));
     void squashDueToMemStall(int stage_num, InstSeqNum seq_num, ThreadID tid);    
 
     void removePipelineStalls(ThreadID tid);
@@ -587,23 +594,17 @@ class InOrderCPU : public BaseCPU
 
     FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
 
+    CCReg readCCReg(RegIndex reg_idx, ThreadID tid);
+
     void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
 
     void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
 
     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 
-    RegType inline getRegType(RegIndex reg_idx)
-    {
-        if (reg_idx < TheISA::FP_Base_DepTag)
-            return IntType;
-        else if (reg_idx < TheISA::Ctrl_Base_DepTag)
-            return FloatType;
-        else
-            return MiscType;
-    }
+    void setCCReg(RegIndex reg_idx, CCReg val, ThreadID tid);
 
-    RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
+    RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
 
     /** Reads a miscellaneous register. */
     MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
@@ -854,9 +855,6 @@ class InOrderCPU : public BaseCPU
     /** Pointers to all of the threads in the CPU. */
     std::vector<Thread *> thread;
 
-    /** Whether or not the CPU should defer its registration. */
-    bool deferRegistration;
-
     /** Per-Stage Instruction Tracing */
     bool stageTracing;