/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
#include "arch/types.hh"
#include "base/statistics.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "sim/eventq.hh"
#include "sim/process.hh"
+class CacheUnit;
class ThreadContext;
class MemInterface;
class MemObject;
/* Destructor */
~InOrderCPU();
+ /** Return a reference to the data port. */
+ virtual CpuPort &getDataPort() { return dataPort; }
+
+ /** Return a reference to the instruction port. */
+ virtual CpuPort &getInstPort() { return instPort; }
+
/** CPU ID */
int cpu_id;
/** Overall CPU status. */
Status _status;
private:
+
+ /**
+ * CachePort class for the in-order CPU, interacting with a
+ * specific CacheUnit in the pipeline.
+ */
+ class CachePort : public CpuPort
+ {
+
+ private:
+ /** Pointer to cache unit */
+ CacheUnit *cacheUnit;
+
+ public:
+ /** Default constructor. */
+ CachePort(CacheUnit *_cacheUnit);
+
+ protected:
+
+ /** Timing version of receive */
+ bool recvTiming(PacketPtr pkt);
+
+ /** Handles doing a retry of a failed timing request. */
+ void recvRetry();
+ };
+
/** Define TickEvent for the CPU */
class TickEvent : public Event
{
void process();
/** Returns the description of the tick event. */
- const char *description();
+ const char *description() const;
};
/** The tick event used for scheduling CPU ticks. */
void process();
/** Returns the description of the CPU event. */
- const char *description();
+ const char *description() const;
/** Schedule Event */
void scheduleEvent(int delay);
CPUEventPri event_pri = InOrderCPU_Pri);
public:
+
+ /** Width (processing bandwidth) of each stage */
+ int stageWidth;
+
/** Interface between the CPU and CPU resources. */
ResourcePool *resPool;
DynInstPtr dummyInst[ThePipeline::MaxThreads];
DynInstPtr dummyBufferInst;
DynInstPtr dummyReqInst;
+ DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
/** Used by resources to signify a denied access to a resource. */
ResourceRequest *dummyReq[ThePipeline::MaxThreads];
- /** Identifies the resource id that identifies a fetch
- * access unit.
- */
- unsigned fetchPortIdx;
-
- /** Identifies the resource id that identifies a ITB */
- unsigned itbIdx;
-
- /** Identifies the resource id that identifies a data
- * access unit.
- */
- unsigned dataPortIdx;
-
- /** Identifies the resource id that identifies a DTB */
- unsigned dtbIdx;
-
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
- /** Width (processing bandwidth) of each stage */
- int stageWidth;
-
/** Program Counters */
TheISA::PCState pc[ThePipeline::MaxThreads];
TheISA::TLB *getITBPtr();
TheISA::TLB *getDTBPtr();
+ Decoder *getDecoderPtr();
+
/** Accessor Type for the SkedCache */
typedef uint32_t SkedID;
SkedCacheIt endOfSkedIt;
ThePipeline::RSkedPtr frontEndSked;
+ ThePipeline::RSkedPtr faultSked;
/** Add a new instruction schedule to the schedule cache */
void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
}
ThePipeline::RSkedPtr createFrontEndSked();
+ ThePipeline::RSkedPtr createFaultSked();
ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
class StageScheduler {
}
};
+ private:
+
+ /** Data port. Note that it has to appear after the resPool. */
+ CachePort dataPort;
+
+ /** Instruction port. Note that it has to appear after the resPool. */
+ CachePort instPort;
+
public:
/** Registers statistics. */
/** Initialize the CPU */
void init();
- /** Get a Memory Port */
- Port* getPort(const std::string &if_name, int idx = 0);
-
-#if FULL_SYSTEM
/** HW return from error interrupt. */
Fault hwrei(ThreadID tid);
bool simPalCheck(int palFunc, ThreadID tid);
+ void checkForInterrupts();
+
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Update the Virt and Phys ports of all ThreadContexts to
- * reflect change in memory connections. */
- void updateMemPorts();
-
/** Check if this address is a valid instruction address. */
bool validInstAddr(Addr addr) { return true; }
/** Check if this address is a valid data address. */
bool validDataAddr(Addr addr) { return true; }
-#else
+
/** Schedule a syscall on the CPU */
void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
int delay = 0);
/** Executes a syscall.*/
void syscall(int64_t callnum, ThreadID tid);
-#endif
/** Schedule a trap on the CPU */
void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
void deactivateThread(ThreadID tid);
/** Schedule a thread suspension on the CPU */
- void suspendContext(ThreadID tid, int delay = 0);
+ void suspendContext(ThreadID tid);
/** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
void suspendThread(ThreadID tid);
/** Schedule a thread halt on the CPU */
- void haltContext(ThreadID tid, int delay = 0);
+ void haltContext(ThreadID tid);
/** Halt Thread, Remove from Active Thread List, Place Thread on Halted
* Threads List
*/
std::queue<ListIt> removeList;
+ bool trapPending[ThePipeline::MaxThreads];
+
/** List of all the cpu event requests that will be removed at the end of
* the current cycle.
*/
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
-#if FULL_SYSTEM
virtual void wakeup();
-#endif
- // LL/SC debug functionality
+ /* LL/SC debug functionality
unsigned stCondFails;
unsigned readStCondFailures()
unsigned setStCondFailures(unsigned st_fails)
{ return stCondFails = st_fails; }
+ */
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(ThreadID tid = 0)
}
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInstructions() const
+ virtual Counter totalInsts() const
{
Counter total(0);
return total;
}
-#if FULL_SYSTEM
+ /** Count the Total Ops Committed in the CPU. */
+ virtual Counter totalOps() const
+ {
+ Counter total(0);
+
+ for (ThreadID tid = 0; tid < (ThreadID)thread.size(); tid++)
+ total += thread[tid]->numOp;
+
+ return total;
+ }
+
/** Pointer to the system. */
System *system;
- /** Pointer to physical memory. */
- PhysicalMemory *physmem;
-#endif
-
/** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
unsigned resReqCount;
#endif
- /** Counter of how many stages have completed switching out. */
- int switchCount;
+ Addr lockAddr;
- /** Pointers to all of the threads in the CPU. */
- std::vector<Thread *> thread;
+ /** Temporary fix for the lock flag, works in the UP case. */
+ bool lockFlag;
- /** Pointer to the icache interface. */
- MemInterface *icacheInterface;
+ /** Counter of how many stages have completed draining */
+ int drainCount;
- /** Pointer to the dcache interface. */
- MemInterface *dcacheInterface;
+ /** Pointers to all of the threads in the CPU. */
+ std::vector<Thread *> thread;
/** Whether or not the CPU should defer its registration. */
bool deferRegistration;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
+ /** Stat for the number of committed ops per thread. */
+ Stats::Vector committedOps;
+
/** Stat for the number of committed instructions per thread. */
Stats::Vector smtCommittedInsts;
projects / gem5.git / blobdiff